MC100EPT23 Datasheet, PDF (5/8 Pages) ON Semiconductor – Dual Differential LVPECL to LVTTL Translator

MC100EPT23
ORDERING INFORMATION
Device
Package
Shipping^†
MC100EPT23D
SOIC−8
98 Units / Rail
MC100EPT23DG
SOIC−8
(Pb−Free)
98 Units / Rail
MC100EPT23DR2
SOIC−8
2500 / Tape & Reel
MC100EPT23DR2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
MC100EPT23DT
TSSOP−8
100 Units / Rail
MC100EPT23DTG
TSSOP−8
(Pb−Free)
100 Units / Rail
MC100EPT23DTR2
TSSOP−8
2500 / Tape & Reel
MC100EPT23DTR2G
TSSOP−8
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D − ECL Clock Distribution Techniques
AN1406/D − Designing with PECL (ECL at +5.0 V)
AN1503/D − ECLinPSt I/O SPiCE Modeling Kit
AN1504/D − Metastability and the ECLinPS Family
AN1568/D − Interfacing Between LVDS and ECL
AN1642/D − The ECL Translator Guide
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices
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