FS7140 Datasheet, PDF (5/17 Pages) ON Semiconductor – Programmable Phase-Locked Loop Clock Generator

FS7140, FS7145
Table 4. DC ELECTRICAL SPECIFICATIONS (Note 1)
Parameter
Symbol
Conditions/Description
Min
Typ
Max
Units
CLOCK OUTPUTS, CMOS MODE (CLKN, CLKP)
Low−level output sink current
I_OL
CLOCK OUTPUTS, PECL MODE (CLKN, CLKP)
V_O = 0.4 V
−35
mA
IPRG bias voltage
V_IPRG
V_IPRG will be clamped to this level
when a resistor is connected from
VDD to IPRG
V_DD/3
V
IPRG bias current
Sink current to IPRG current ratio
I_IPRG
I_IPRG − (V_VDD − V_IPRG) / R_SET
3.5
mA
13
Tristate output current
I_Z
−10
10
mA
1. Unless otherwise stated, V_DD = 3.3 V ± 10%, no load on any output, and ambient temperature range T_A = 0°C to 70°C. Parameters denoted
with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characteriza-
tion data are ± 3s from typical. Negative currents indicate flows out of the device.
Table 5. AC TIMING SPECIFICATIONS (Note 2)
Parameter
Symbol
Conditions/Description
Min
Typ
Max
Units
OVERALL
Output frequency*
f_o(max)
CMOS outputs
PECL outputs
0
150
MHz
0
300
VCO frequency*
f_VCO
CMOS mode rise time*
t_r
CMOS mode fall time*
t_f
PECL mode rise time*
t_r
PECL mode fall time*
t_f
REFERENCE FREQUENCY INPUT (REF)
C_L = 7 pF
C_L = 7 pF
C_L = 7 pF; R_L = 65 ohm
C_L = 7 pF; R_L = 65 ohm
40
400
MHz
1
ns
1
ns
1
ns
1
ns
Input frequency
Reference high time
Reference low time
SYNC CONTROL INPUT (SYNC)
F_REF
t_REHF
t_REFL
80
MHz
3
ns
3
ns
Sync high time
t_SYNCH For orderly CLK stop/start
3
Sync low time
t_SYNCL For orderly CLK stop/start
3
CLOCK OUTPUT (CLKN, CLKP)
T_CLK
Duty cycle (CMOS mode)*
Measured at 1.4 V
50
%
Duty cycle (PECL mode)*
Jitter, long term (s_y(t))*
Measured at zero crossings of
(V_CLKP − V_CLKN)
50
%
t_j(LT)
For valid programming solutions. Long-term (or cumulative) jitter specified is
ps
RMS position error of any edge compared with an ideal clock generated from
the same reference frequency. It is measured with a time interval analyzer us-
ing a 500 microsecond window, using statistics gathered over 1000 samples.
FREF/NREF > 1000 kHz
25
ps
FREF/NREF ^ 500 kHz
50
ps
FREF/NREF ^ 250 kHz
100
ps
FREF/NREF ^ 125 kHz
190
ps
FREF/NREF ^ 62.5 kHz
240
ps
FREF/NREF ^ 31.5 kHz
300
ps
Jitter, period (peak−peak)*
t_j(DP)
40 MHz < VCO frequency < 100 MHz
VCO frequency > 100 MHz
75
ps
50
ps
2. Unless otherwise stated, V_DD = 3.3 V ± 10%, no load on any output, and ambient temperature range T_A = 0°C to 70°C. Parameters denoted
with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization
data are ± 3s from typical.
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