ENA2269 Datasheet, PDF (5/23 Pages) ON Semiconductor – 8M-bit (1024K  8) Serial Flash Memory

Figure 1 Pin Assignments
CS ₁
8 ^VDD
SO/SIO1 2
7 ^HOLD
WP ₃
6 ^SCK
VSS 4
5 ^SI/SIO0
Top view
VSON8T (LE25S81QE)
LE25S81QE
Table 1 Pin Description
Symbol
Pin Name
SCK
Serial clock
SI/SIO0
SO/SIO1
CS
Serial data input
/ Serial data input output
Serial data input
/ Serial data input output
Chip select
WP
HOLD
VDD
VSS
Write protect
Hold
Power supply
Ground
Description
This pin controls the data input/output timing.
The input data and addresses are latched synchronized to the rising edge of the serial clock, and the data is
output synchronized to the falling edge of the serial clock.
The data and addresses are input from this pin, and latched internally synchronized to the rising edge of the
serial clock. It changes into the output pin at Dual Output and it changes into the input output pin at Dual I/O. *1
The data stored inside the device is output from this pin synchronized to the falling edge of the serial clock. It
changes into the output pin at Dual Output and it changes into the input output pin at Dual I/O. *1
The device becomes active when the logic level of this pin is low; it is deselected and placed in standby status
when the logic level of the pin is high.
The status register write protect (SRWP) takes effect when the logic level of this pin is low.
Serial communication is suspended when the logic level of this pin is low.
This pin supplies the 1.65 to 1.95V supply voltage.
This pin supplies the 0V supply voltage.
*1: Dual Output Read and Dual I/O Read are not supported on LE25S81QE.
Figure 2 Block Diagram
ADDRESS
BUFFERS
&
LATCHES
X-
DECODER
8M Bit
Flash EEPROM
Cell Array
Y-DECODER
CONTROL
LOGIC
I/O BUFFERS
&
DATA LATCHES
SERIAL INTERFACE
CS SCK SI/SIO0 SO/SIO1 WP HOLD
No.A2269-5/23