CS5323_06 Datasheet, PDF (5/16 Pages) ON Semiconductor – Three−Phase Buck Controller with 5−Bit DAC

CS5323
ELECTRICAL CHARACTERISTICS (continued) (0°C < T_A < 70°C; 0°C < T_J < 85°C; 4.7 V < V_CC < 14 V; C_GATE = 100 pF,
R_{R(OSC) =} 53.6 k, C_COMP = 0.1 μF, C_REF = 0.1μF, DAC Code 10000, C_VCC = 0.1 μF, I_LIM ≥ 1.0 V; unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Voltage Feedback Error Amplifier
V_FB Bias Current (Note 2)
COMP Source Current
0.9 V < V_FB < 1.9 V
17.6
19.0
20.6
μA
COMP = 0.5 V to 2.0 V; V_FB = 1.8 V; DAC = 00000
15
30
60
μA
COMP Sink Current
COMP = 0.5 V to 2.0 V; V_FB = 1.9 V; DAC = 00000
15
30
60
μA
COMP Discharge Threshold Voltage
−
0.20
0.27
0.34
V
Transconductance
Output Impedance
−10 μA < I_COMP < +10 μA
−
−
32
−
2.5
−
mmho
−
MΩ
Open Loop DC Gain
Note 3
60
90
−
dB
Unity Gain Bandwidth
0.01 μF
−
400
−
kHz
PSRR @ 1 kHz
−
−
70
−
dB
COMP Max Voltage
V_FB = 1.8 V; COMP Open; DAC = 00000
2.4
2.7
−
V
COMP Min Voltage
Hiccup Latch Discharge Current
COMP Discharge Ratio
V_FB = 1.9 V; COMP Open; DAC = 00000
−
−
−
0.1
2.0
5.0
4.0
6.0
0.2
V
10
μA
10
−
PWM Comparators
Minimum Pulse Width
Channel Start Up Offset
Measured from CSx to GATE(H) with 60 mV step
−
between CSx and CS_REF
350
500
ns
V(CS1) = V(CS2) = V(CS3) = V(V_FB)
V(CS_REF) = 0 V; Measure V(COMP) when
GATE (H) 1, 2 switch high
0.3
0.4
0.5
V
GATEs
High Voltage
Low Voltage
Rise Time GATE
Fall Time GATE
Oscillator
Switching Frequency
Switching Frequency
Switching Frequency
R_OSC Voltage
Phase Delay
Measure V_CC − GATEx, I_GATEx = 1.0 mA
Measure GATEx, I_GATEx = 1.0 mA
1.0 V < GATE < 8.0 V; V_CC = 10 V
8.0 V > GATE > 1.0 V; V_CC = 10 V
R_OSC = 53.6 k
Note 3 R_OSC = 32.4 k
Note 3 R_OSC = 16.2 k
−
Rising edge only
−
1.2
2.1
V
−
0.25
0.50
V
−
30
60
ns
−
30
60
ns
220
250
280
kHz
300
400
500
kHz
600
800
1000
kHz
−
1.00
−
V
105
120
135
deg
Adaptive Voltage Positioning
V_DRP Offset
Maximum V_DRP Voltage
CS1 = CS2 = CS3 = CS_REF, V_FB = COMP
Measure V_DRP − COMP
|(CS1 = CS2 = CS3) − C_REF| = 50 mV,
V_FB = COMP, Measure V_DRP − COMP
Current Share Amp to V_DRP Gain
−
2. The V_FB Bias Current changes with the value of R_OSC per Figure 4.
3. Guaranteed by design. Not tested in production.
−20
−
360
465
2.7
3.0
20
mV
570
mV
3.5
V/V
http://onsemi.com
5