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CS3842B Datasheet, PDF (5/8 Pages) Cherry Semiconductor Corporation – Off-Line Current Mode PWM Control Circuit Off-Line Current Mode PWM Control Circuit
VOSC
OSC
RESET
EA Output
Switch
Current
VCC
IOUT
VOUT
Figure 2: Timing Diagram for key CS-384XB parameters
Figure 3: Oscillator
cycle tends to exceed the maximum allowed, to prevent
transformer saturation in some power supplies, the inter-
nal oscillator waveform provides the maximum duty cycle
clamp as programmed by the selection of oscillator timing
components.
Setting the Oscillator
The oscillator timing capacitor, CT, is charged by VREF
through RT and discharged by an internal current source
(Figure 3). During the discharge time, the internal clock
signal blanks out the output to the Low state, thus provid-
ing a user selected maximum duty cycle clamp.
Charge and discharge times are determined by the general
formulas:
( ) tc = RTCT ln
VREF – Vlower
VREF – Vupper
( ) td = RTCT ln
VREF – Id RT –Vlower
VREF – Id RT – Vupper
VREF
RT
OSC
CT
Gnd
Vupper
Vlower
tc
Sawtooth Mode
LARGE RT (≈10kΩ)
td
VOSC
Triangular Mode
SMALL RT (≈700kΩ)
Internal Clock
VREF
Substituting in typical values for the parameters in the
above formulas:
then
VREF = 5.0V, Vupper = 2.7V, Vlower = 1.0V, Id = 8.3mA,
tc ≈ 0.5534RTCT
( ) td = RTCT ln
2.3 – 0.0083 RT
4.0 – 0.0083 RT
The frequency and maximum duty cycle can be deter-
mined from the Typical Performance Characteristics
graphs.
Grounding
High peak currents associated with capacitive loads neces-
sitate careful grounding techniques. Timing and bypass
capacitors should be connected close to ground in a single
point ground.
The transistor and 5kΩ potentiometer are used to sample
the oscillator waveform and apply an adjustable ramp to
Sense.
Internal Clock
Figure 3: Oscillator Timing Network and parameters
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