CAT5419_13 Datasheet, PDF (5/15 Pages) ON Semiconductor – Dual Digital Potentiometer (POT)

CAT5419
Table 7. A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Min
Typ
f_SCL
Clock Frequency
T_I (Note 8)
Noise Suppression Time Constant at SCL, SDA Inputs
t_AA
SLC Low to SDA Data Out and ACK Out
t_BUF (Note 8)
Time the bus must be free before a new transmission can start
1.2
t_HD:STA
Start Condition Hold Time
0.6
t_LOW
Clock Low Period
1.2
t_HIGH
Clock High Period
0.6
t_SU:STA
Start Condition Setup Time (for a Repeated Start Condition)
0.6
t_HD:DAT
Data in Hold Time
0
t_SU:DAT
Data in Setup Time
100
t_R (Note 8)
SDA and SCL Rise Time
t_F (Note 8)
SDA and SCL Fall Time
t_SU:STO
Stop Condition Setup Time
0.6
t_DH
Data Out Hold Time
50
Max
Units
400
kHz
50
ns
0.9
ms
ms
ms
ms
ms
ms
ns
ns
0.3
ms
300
ns
ms
ns
Table 8. POWER UP TIMING (Note 8) (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Min
Typ
t_PUR
Power-up to Read Operation
t_PUW
Power-up to Write Operation
8. This parameter is tested initially and after a design or process change that affects the parameter.
Max
Units
1
ms
1
ms
Table 9. WRITE CYCLES LIMITS (Note 9)
Symbol
Parameter
Max
Units
t_WR
Write Cycle Time
5
ms
9. The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
Table 10. RELIABILITY CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Reference Test Method
Min
Typ Max
N_END (Note 10)
Endurance
MIL−STD−883, Test Method 1033
1,000,000
T_DR (Note 10)
Data Retention
MIL−STD−883, Test Method 1008
100
V_ZAP (Note 10)
ESD Susceptibility MIL−STD−883, Test Method 3015
2,000
I_LTH (Notes 10, 11)
Latch-up
JEDEC Standard 17
100
10. This parameter is tested initially and after a design or process change that affects the parameter.
11. t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified operation can be initiated.
Units
Cycles/Byte
Years
Volts
mA
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