CAT5221WI-25 Datasheet, PDF(5/16 Page) ON Semiconductor – Dual Digitally Programmable Potentiometer with 64 Taps and I2C Interface

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CAT5221WI-25 Datasheet, PDF (5/16 Pages) ON Semiconductor – Dual Digitally Programmable Potentiometer with 64 Taps and I2C Interface

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CAT5221

WRITE CYCLE LIMITS

Over recommended operating conditions unless otherwise stated.

Symbol Parameter

tWR

Write Cycle Time

Min

Typ Max Units

The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase

cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the

device does not respond to its slave address.

RELIABILITY CHARACTERISTICS

Over recommended operating conditions unless otherwise stated.

Symbol

NEND(1)

TDR(1)

VZAP(1)

ILTH(1)(2)

Parameter

Endurance

Data Retention

ESD Susceptibility

Latch-Up

Reference Test Method

Min

Typ Max

Units

MIL-STD-883, Test Method 1033 1,000,000

Cycles/Byte

MIL-STD-883, Test Method 1008

100

Years

MIL-STD-883, Test Method 3015

2000

Volts

JEDEC Standard 17

100

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.

Figure 1. Bus Timing

tHIGH

tLOW

SCL

tSU:STA

tHD:DAT

tHD:STA

tSU:DAT

SDA IN

SDA OUT

tAA

tDH

tSU:STO

tBUF

Figure 2. Write Cycle Timing

SCL

SDA

8TH BIT

BYTE n

ACK

Figure 3. Start/Stop Timing

SDA

SCL

Characteristics subject to change without notice

START BIT

tWR

STOP

CONDITION

START

CONDITION

ADDRESS

STOP BIT

Doc. No. MD-2113 Rev. L

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