CAT28C16A Datasheet, PDF (5/10 Pages) Catalyst Semiconductor – 16K-Bit CMOS PARALLEL E2PROM

CAT28C16A
DEVICE OPERATION
Read
Data stored in the CAT28C16A is transferred to the data bus when WE is held high, and both OE and CE are held low. The
data bus is set to a high impedance state when either CE or OE goes high. This 2−line control architecture can be used to
eliminate bus contention in a system environment.
t_RC
ADDRESS
t_CE
CE
OE
WE
DATA OUT
t_OE
V_IH
t_OLZ
t_LZ
HIGH−Z
t_AA
t_OH
DATA VALID
Figure 4. Read Cycle
t_OHZ
t_HZ
DATA VALID
ADDRESS
CE
t_AS
t_AH
t_CS
t_WC
t_CH
OE
WE
DATA OUT
t_OES
t_WP
HIGH−Z
t_OEH
t_DL
DATA IN
DATA VALID
t_DS
t_DH
Figure 5. Byte Write Cycle [WE Controlled]
Byte Write
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either WE
or CE, with the address input being latched on the falling
edge of WE or CE, whichever occurs last. Data, conversely,
is latched on the rising edge of WE or CE, whichever occurs
first. Once initiated, a byte write cycle automatically erases
the addressed byte and the new data is written within 10 ms.
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