CAT1161WI-30-G Datasheet, PDF (5/13 Pages) ON Semiconductor – Supervisory Circuits with I2C Serial CMOS EEPROM, Precision Reset Controller

CAT1161, CAT1162
PIN DESCRIPTION
WP: WRITE PROTECT
If the pin is tied to VCC the entire memory array becomes
Write Protected (READ only). When the pin is tied to GND
or left floating normal read/write operations are allowed to
the device.
RESET/RESET: RESET I/O
These are open drain pins and can be used as reset trigger
inputs. By forcing a reset condition on the pins the device
will initiate and maintain a reset condition. The RESET pin
must be connected through a pulldown resistor, and the
RESET pin must be connected through a pull−up resistor.
SDA: SERIAL DATA ADDRESS
The bidirectional serial data/address pin is used to transfer
all data into and out of the device. The SDA pin is an open
drain output and can be wire−ORed with other open drain or
open collector outputs.
If there is no transition on the SDA for more than
1.6 seconds, the watchdog timer times out.
SCL: Serial Clock
Serial clock input.
DEVICE OPERATION
Reset Controller Description
The CAT1161/2 precision RESET controller ensures
correct system operation during brownout and power
up/down conditions. It is configured with open drain
RESET outputs. During power−up, the RESET outputs
remain active until V_CC reaches the V_TH threshold and will
continue driving the outputs for approximately 200 ms
(t_PURST) after reaching V_TH. After the t_PURST timeout
interval, the device will cease to drive the reset outputs. At
this point the reset outputs will be pulled up or down by their
respective pull up/down resistors. During power−down, the
RESET outputs will be active when V_CC falls below V_TH.
The RESET outputs will be valid so long as V_CC is > 1.0 V
(V_RVALID).
The RESET pins are I/Os; therefore, the CAT1161/2 can
act as a signal conditioning circuit for an externally applied
manual reset. The inputs are edge triggered; that is, the
RESET input in the CAT1161/2 will initiate a reset timeout
after detecting a low to high transition and the RESET input
will initiate a reset timeout after detecting a high to low
transition.
Watchdog Timer
The Watchdog Timer provides an independent protection
for microcontrollers. During a system failure, the CAT1161
will respond with a reset signal after a time−out interval of
1.6 seconds for a lack of activity. The CAT1161 is designed
with the Watchdog Timer feature on the SDA input. If the
microcontroller does not toggle the SDA input pin within 1.6
seconds, the Watchdog Timer times out. This will generate
a reset condition on reset outputs. The Watchdog Timer is
cleared by any transition on SDA.
As long as reset signal is asserted, the Watchdog Timer
will not count and will stay cleared.
The CAT1162 does not have a Watchdog.
t
GLITCH
V_TH
V_{RVA LI D}
V_CC
t _PURS T
t _RPD
t _PURS T
RESET
t _RPD
RESET
Figure 1. RESET Output Timing
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