ADT7476_16 Datasheet, PDF (5/68 Pages) ON Semiconductor – Remote Thermal Controller and Voltage Monitor

ADT7476
Table 4. ELECTRICAL CHARACTERISTICS (T_A = T_MIN to T_MAX, V_CC = V_MIN to V_MAX, unless otherwise noted.) (Note 1)
Parameter
Conditions
Min
Typ
Max
Unit
Digital Input Logic Levels (THERM) ADTL+
Input High Voltage, V_IH
Input Low Voltage, V_IL
Digital Input Current
Input High Current, I_IH
Input Low Current, I_IL
Input Capacitance, C_IN
Serial Bus Timing (See Figure 2)
V_IN = V_CC
V_IN = 0 V
0.75 x V_CCP
−
−
−
−
V
0.8
V
−
±1
−
mA
−
±1
−
mA
−
5.0
−
pF
Clock Frequency, f_SCLK
10
−
400
kHz
Glitch Immunity, t_SW
−
−
50
ns
Bus Free Time, t_BUF
4.7
−
−
ms
SCL Low Time, t_LOW
4.7
−
−
ms
SCL High Time, t_HIGH
4.0
−
50
ms
SCL, SDA Rise Time, t_r
−
−
1,000
ns
SCL, SDA Fall Time, t_f
−
−
300
ms
Data Setup Time, t_SU;DAT
250
−
−
ns
Detect Clock Low Timeout, t_TIMEOUT
Can be Optionally Disabled
15
−
35
ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. All voltages are measured with respect to GND, unless otherwise specified. Typical voltages are T_A = 25°C and represent a parametric norm.
Logic inputs accept input high voltages up to V_MAX, even when the device is operating down to V_MIN. Timing specifications are tested at logic
levels of V_IL = 0.8 V for a falling edge, and V_IH = 2.0 V for a rising edge.
2. SMBus timing specifications are guaranteed by design and are not production tested.
SCL
SDA
t_BUF
P
S
t _LOW
t_R
t_{HD; STA}
t_{HD; DAT}
t_F
t_HIGH
t_{SU; DAT}
t _{HD; STA}
t_{SU; STA}
S
Figure 2. Serial Bus Timing Diagram
t_{SU; STO}
P
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