NOIV1SE5000A Datasheet, PDF (44/70 Pages) ON Semiconductor – VITA 5000 5.3 Megapixel 75 FPS Global Shutter CMOS Image Sensor

NOIV1SN5000A
REGISTER MAP
Table 35. REGISTER MAP
Address
Offset
Address
Bit Field
Chip ID [Block Offset: 0]
0
0
1
1
2
2
[15:0]
[3:0]
[1:0]
Register Name
chip_id
id
reserved
reserved
chip_configuration
Reset Generator [Block Offset: 8]
0
8
[3:0]
soft_reset_pll
pll_soft_reset
[7:4]
pll_lock_soft_reset
1
9
soft_reset_cgen
[3:0]
cgen_soft_reset
2
10
soft_reset_analog
[3:0]
mux_soft_reset
[7:4]
afe_soft_reset
[11:8]
ser_soft_reset
PLL [Block Offset: 16]
0
16
power_down
[0]
pwd_n
[1]
enable
[2]
bypass
1
17
config
Default Default
(Hex) (Dec)
Description
0x5632
0x5632
0x0000
0x0000
0x0000
0x0
22066
22066
0
0
0
0
ON Semiconductor chip ID
Reserved
Configure as per part number:
NOIV1SN5000A-QDC: 0x0
NOIV1SE5000A-QDC: 0x1
0x099
0x9
0x9
0x09
0x9
0x0999
0x9
0x9
0x9
153
9
9
9
9
2457
9
9
9
PLL reset
0x9: Soft Reset State
Others: Operational
PLL Lock Detect Reset
0x9: Soft Reset State
Others: Operational
Clock Generator Reset
0x9: Soft Reset State
Others: Operational
Column MUX Reset
0x9: Soft Reset State
Others: Operational
AFE Reset
0x9: Soft Reset State
Others: Operational
Serializer Reset
0x9: Soft Reset State
Others: Operational
0x0004
0x0
0x0
0x1
0x2113
4
0
0
1
8467
PLL Power Down
‘0’ = Power Down,
‘1’ = Operational
PLL Enable
‘0’ = disabled,
‘1’ = enabled
PLL Bypass
‘0’ = PLL Active,
‘1’ = PLL Bypassed
Type
RO
RO
RW
[0]:
color
RW
RW
RW
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