NVD6416ANLT4G Datasheet, PDF (4/7 Pages) ON Semiconductor – N-Channel Power MOSFET 100 V, 19 A, 74 m

NTD6416ANL, NVD6416ANL
1400
1200
10
100
T_J = 25°C
Q_T
V_GS = 0 V
8
80
1000
800
C_iss
600
6
V_DS
V_GS
60
4 Q_gs
Q_gd
40
400
2
200
C_oss
0 ^Crss
0
V_DS = 80 V ²⁰
I_D = 19 A
T_J = 25°C ₀
0 10 20 30 40 50 60 70 80 90 100 0
5
10
15
20
25
V_DS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
1000
100
V_DS = 80 V
I_D = 19 A
V_GS = 10 V
t_d(off)
t_f
Q_g, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source Voltage and
Drain−to−Source Voltage versus Total Charge
20
T_J = 25°C
V_GS = 0 V
15
10
t_r
10
t_d(on)
5
1
1
10
100
R_G, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
100
10 mS
10
100 mS
1 mS
1
V_GS = 10 V
10 mS
dc
SINGLE PULSE
0.1
T_C = 25°C
0.01
0.001
0.1
R_DS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1
10
100
1000
V_DS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
0
0.5 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.0
V_SD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 10. Diode Forward Voltage versus
Current
50
I_D = 18.2 A
40
30
20
10
0
25
50
75
100
125
150 175
V_DS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 12. Resistive Switching Time Variation
versus Gate Resistance
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