NCP81250 Datasheet, PDF (4/18 Pages) ON Semiconductor – Single-Phase Voltage Regulator

NCP81250
Table 1. PIN DESCRIPTION
Pin
Name
Type
Description
1
VRHOT#
Logic Output
VR HOT. Logic low output represents over temperature.
2
SDIO Logic Bidirectional Serial Data IO Port. Data port of SVID interface.
3
ALERT#
Logic Output
ALERT. Open−drain output. Provides a logic low valid alert signal of SVID interface.
4
SCLK
Logic Input
Serial Clock. Clock input of SVID interface.
5, 32,
49
GND
Analog Ground Analog Ground. Ground of internal control circuits. Must be connected to the system ground.
6
VRRDY
Logic Output
Voltage Regulator Ready. Open−drain output. Provides a logic high valid power good output
signal, indicating the regulator’s output is in regulation window.
7,
VIN
11−17,
50
Power Input
Power Supply Input. These pins are the power supply input pins of the device, which are
connected to drain of internal high−side power MOSFET. 22 mF or more ceramic capacitors
must bypass this input to power ground. The capacitors should be placed as close as
possible to these pins.
8
BST
Power
Bootstrap. Provides bootstrap voltage for the high−side gate driver. A 0.1 mF ~ 1 mF ceramic
Bidirectional
capacitor is required from this pin to SW (pin 10). A 1 − 2 W resistor may be employed in
series with the BST cap to reduce switching noise and ringing when needed.
9
GH
Analog Output Gate of High−Side MOSFET. Directly connected with the gate of the high−side power MOSFET.
10
SW
Power Return Switching Node. Provides a return path for integrated high−side gate driver. It is internally
connected to source of high−side MOSFET.
18,
SW
25−29,
51
Power Output
Switch Node. Pins to be connected to an external inductor. These pins are interconnection
between internal high−side MOSFET and low−side MOSFET.
19−24 PGND
Power Ground
Power Ground. These pins are the power supply ground pins of the device, which are
connected to source of internal low−side power MOSFET. Must be connected to the system
ground.
30
GL
Analog Output Gate of Low−Side MOSFET. Directly connected with the gate of the low−side power MOSFET.
31 VBOOT
Analog Input
Boot−Up Voltage. A resistor from this pin to ground programs SVID address.
33
VCCP
Analog Power Voltage Supply of Gate Driver. Power supply input pin of internal gate driver. A 4.7 mF or
larger ceramic capacitor bypasses this input to ground. This capacitor should be placed as
close as possible to this pin.
34 TSENSE
Analog
Temperature Sense. An external temperature sense network is connected to this pin.
35
IMAX
Analog Input
Current Maximum. A resistor from this pin to ground programs IMAX.
36
IOUT
Analog Output OUT Current Monitor. Provides output signal representing output current by connecting a
resistor from this pin to ground. Shorting this pin to ground disables IMON function.
37
ILIM
Analog Output Limit of Current. A resistor from this pin to CSCOMP programs over−current threshold with
inductor current sense.
38 CSCOMP Analog Output Current Sense COMP. Output pin of current sense amplifier.
39 CSSUM
Analog Input
Current Sense SUM. Inverting input of current sense amplifier.
40 CSREF
Analog Input
Current Sense Reference. Non−Inverting input of current sense amplifier.
41
FREQ
Analog Input
Frequency. A resistor from this pin to ground programs switching frequency.
42
COMP
Analog
Compensation. Output pin of error amplifier.
43
FB
Analog Input
Feedback. Inverting input to error amplifier.
44 DIFFOUT Analog Output Differential Amplifier Output. Output pin of differential voltage sense amplifier.
45
VSN
Analog Input
Voltage Sense Negative Input. Inverting input of differential voltage sense amplifier. It is
also used for DVID feed forward function with an external resistor.
46
VSP
Analog Input
Voltage Sense Positive Input. Non−inverting input of differential voltage sense amplifier.
47
VCC
Analog Power Voltage Supply of Controller. Power supply input pin of control circuits. A 1 mF or larger
ceramic capacitor bypasses this input to ground. This capacitor should be placed as close as
possible to this pin.
48
EN
Logic Input
Enable. Logic high enables the device and logic low makes the device in standby mode.
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