NCP1652DR2G Datasheet, PDF (4/34 Pages) ON Semiconductor – High-Efficiency Single Stage Power Factor Correction and Step-Down Controller

NCP1652, NCP1652A
PIN FUNCTION DESCRIPTION
Pin
16 Pin 20 Pin
Symbol
1
1
C_T
2
2
RAMP COMP
3
3
4
4
AC IN
FB
5
5
VFF
6
6
CM
7
NC
8
NC
7
9
AC COMP
8
10
9
11
10
12
11
13
12
14
Latch
Rdelay
I_AVG
I_Spos
V_CC
13
15
14
16
15
17
18
19
16
20
OUTA
OUTB
GND
NC
NC
HV
Description
An external timing capacitor (C_T) sets the oscillator frequency. A sawtooth between 0.2 V and 4
V sets the oscillator frequency and the gain of the multiplier.
A resistor (R_RC) between this pin and ground adjust the amount of ramp compensation that is
added to the current signal. Ramp compensation is required to prevent subharmonic oscilla-
tions. This pin should not be left open.
The scaled version of the full wave rectified input ac wave is connected to this pin by means of
a resistive voltage divider. The line voltage information is used by the multiplier.
An error signal from an external error amplifier circuit is fed to this pin via an optocoupler or
other isolation circuit. The FB voltage is a proportional of the load of the converter. If the voltage
on the FB pin drops below V_SSKIP the controller enters Soft−Skip™ to reduce acoustic noise.
Feedforward input. A scaled version of the filtered rectified line voltage is applied by means of a
resistive divider and an averaging capacitor. The information is used by the Reference Generat-
or to regulate the controller.
Multiplier output. A capacitor is connected between this pin and ground to filter the modulated
output of the multiplier.
Sets the pole for the ac reference amplifier. The reference amplifier compares the low fre-
quency component of the input current to the ac reference signal. The response must be slow
enough to filter out most of the high frequency content of the current signal that is injected from
the current sense amplifier, but fast enough to cause minimal distortion to the line frequency
information. The pin should not be left open.
Latch−Off input. Pulling this pin below 1.0 V (typical) or pulling it above 7.0 V (typical) latches
the controller. This input can be used to implement an overvoltage detector, an overtemperature
detector or both. Refer to Figure 69 for a typical implementation.
A resistor between this pin and ground sets the non−overlap time delay between OUTA and
OUTB. The delay is adjusted to prevent cross conduction between the primary MOSFET and
synchronous rectification MOSFET or optimize the resonant transition in an active clamp stage.
An external resistor and capacitor connected from this terminal to ground, to set and stabilizes
the gain of the current sense amplifier output that drives the ac error amplifier.
Positive current sense input. Connects to the positive side of the current sense resistor.
Positive input supply. This pin connects to an external capacitor for energy storage. An internal
current source supplies current from the STARTUP pin V_CC. Once the voltage on V_CC reaches
approximately 15.3 V, the current source turns off and the outputs are enabled. The drivers are
disabled once V_CC reaches approximately 10.3 V. If V_CC drops below 0.85 V (typical), the star-
tup current is reduced to less than 500 mA.
Drive output for the main flyback power MOSFET or IGBT. OUTA has a source resistance of
13 W (typical) and a sink resistance of 8 W (typical).
Secondary output of the PWM Controller. It can be used to drive synchronous rectifier, and
active clamp switch, or both. OUTB has source and sink resistances of 22 W (typical) and 11
(typical), respectively.
Ground reference for the circuit.
Connect the rectified input line voltage directly to this pin to enable the internal startup regulator.
A constant current source supplies current from this pin to the capacitor connected to the V_CC
pin, eliminating the need for a startup resistor. The charge current is typically 5.5 mA. Maximum
input voltage is 500 V.
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