NCP1093 Datasheet, PDF (4/12 Pages) ON Semiconductor – Integrated IEEE 802.3at PoE-PD Interface Controller

NCP1093, NCP1094
Table 1. PIN DESCRIPTION
Pin No.
Name
NCP1093 NCP1094
INRUSH
1
1
CLASS
2
2
DET
3
3
VPORTN1
4
4
VPORTN2
5
5
RTN
6
6
PGOOD
7
7
UVLO
8
−
AUX
−
8
NCLASS_AT
9
9
VPORTP
10
10
Exposed Pad EP
EP
Type
Output
Output
Output,
Open Drain
Ground
Ground
Ground
Output,
Open Drain
Input
Input
Output
Input
Ground
Description
Current limit programming pin. Connect a resistor between INRUSH and
VPORTN.
Classification current programming pin. Connect a resistor between CLASS
and VPORTN.
Detection pin. Connect a 24.9 kW resistor between DET and VPORTP for a
valid PD detection signature.
Negative input power. Connected to the source of the internal pass−switch
Negative input power. Connected to the source of the internal pass−switch
DC−DC controller power return. Connected to the drain of the internal pass−
switch
Open Drain Power Good Indicator. Pin is in HZ mode when the power good
signal is active.
Undervoltage lockout input. Voltage with respect to VPORTN. Connect a resist-
or−divider from VPORTP to UVLO to VPORTNx to set an external UVLO
threshold.
Auxiliary Pin. When this pin is pulled up, the Pass Switch is disabled and allows
a supply transition from PSE to the rear auxiliary supply connected between
VPORTP and RTN.
Active low enable signal used to verify high power operation
Positive input power. Voltage with respect to VPORTN.
Exposed pad should be connected to VPORTN.
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
Max Units
Conditions
VPORTP
Input power supply
−0.3
72
V
Voltage with respect to VPORTN
RTN
Analog ground supply 2 −0.3
72
V
Pass−switch in off−state (voltage with respect to VPORTN)
CLASS
Analog output
−0.3
72
V
Voltage with respect to VPORTN
INRUSH
Analog output
−0.3
3.6
V
Voltage with respect to VPORTN
AUX
Analog input
−0.3
72
V
Voltage with respect to VPORTN
UVLO
Analog input
−0.3
3.6
V
Voltage with respect to VPORTN
PGOOD
Analog output
−0.3
72
V
Voltage with respect to RTN
T_A
T_J
T_J, T_SD
Ambient temperature
Junction temperature
Junction temperature
(Note 1)
−40
85
−
125
−
175
°C
°C
°C
Thermal shutdown condition
T_STG
T_qJA
Storage Temperature
−55
150
°C
Thermal Resistance,
50
Junction to Air (Note 2)
°C/W DFN−10
ESD−HBM
Human Body Model
2
kV
per EIA−JESD22−A114 standard
ESD−CDM Charged Device Model
500
V
per ESD−STM5.3.1 standard
ESD−MM
Machine Model
200
V
per EIA−JESD22−A115−A standard
LU
Latch−up
±100
mA per JEDEC Standard JESD78
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tj−TSD allowed during error conditions only. It is assumed that this maximum temperature condition does not occur more than 1 hour
cumulative during the useful life for reliability reasons.
2. Low qJA is obtained with 2S2P test board (2 signal − 2 plane). High qJA is obtained with double sideboard with minimum pad area and natural
convection. Refer to Jedec JESD51 for details. The exposed pad must be connected to the VPORTN ground pin.
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