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NBXDPA017 Datasheet, PDF (4/7 Pages) ON Semiconductor – 2.5 V / 3.3 V, 156.25 MHz / 312.5MHz LVDS Clock Oscillator
NBXDPA017
Table 7. AC CHARACTERISTICS (VDD = 2.5 V ± 5% or VDD = 3.3 V ± 10%, GND = 0 V, TA = −40°C to +85°C) (Note 4)
Symbol
Characteristic
Conditions
Min.
Typ.
Max.
Units
fCLKOUT
Output Clock Frequency
FSEL = HIGH
FSEL = LOW
156.25
312.5
MHz
Df
Frequency Stability − NBXDPA017
(Note 5)
±50
ppm
FNOISE
Phase−Noise Performance
fCLKout = 156.25 MHz/312.5 MHz
(See Figures 3 and 4)
100 Hz of Carrier
1 kHz of Carrier
10 kHz of Carrier
−107/−102
−121/−115
−127/−121
dBc/Hz
dBc/Hz
dBc/Hz
100 kHz of Carrier
−128/−122
dBc/Hz
1 MHz of Carrier
−135/−129
dBc/Hz
10 MHz of Carrier
−157/−153
dBc/Hz
tjit(F)
tjitter
RMS Phase Jitter
Cycle to Cycle, RMS
Cycle to Cycle, Peak−to−Peak
12 kHz to 20 MHz
1000 Cycles
1000 Cycles
0.5
0.75
ps
4
8
ps
17
35
ps
Period, RMS
10,000 Cycles
2
4
ps
Period, Peak−to−Peak
10,000 Cycles
7
20
ps
tOE/OD
tDUTY_CYCLE
Output Enable/Disable Time
Output Clock Duty Cycle
(Measured at Cross Point)
200
ns
48
50
52
%
tR
Output Rise Time (20% and 80%)
115
400
ps
tF
Output Fall Time (80% and 20%)
115
400
ps
tstart
Start−up Time
Aging
1st Year
1
5
ms
3
ppm
Every Year After 1st
1
ppm
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Measurement taken with outputs terminated with 100 ohm across differential pair. See Figure 5.
5. Parameter guarantees 10 years of aging. Includes initial stability at 25°C, shock, vibration and first year aging.
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