MC74HCT374A_05 Datasheet, PDF (4/8 Pages) ON Semiconductor – Octal 3−State Noninverting D Flip−Flop with LSTTL−Compatible Inputs

MC74HCT374A
AC ELECTRICAL CHARACTERISTICS (V_CC = 5.0 V ± 10%, C_L = 50 pF, Input t_r = t_f = 6.0 ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Guaranteed Limit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Symbol
Parameter
– 55 to 25_C v 85_C v 125_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ fmax Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
30
24
20
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tPHL
Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)
31
39
47
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tPLZ,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ t_PHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 2 and 5)
30
38
45
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPZL,
t_PZH
Maximum Propagation Delay, Output Enable to Q
(Figures 2 and 5)
30
38
45
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tTLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
12
15
18
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Cin Maximum Input Capacitance}
10
10
10
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Cout Maximum Three−State Output Capacitance}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (Output in High−Impedance State)
15
15
15
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Unit
MHz
ns
ns
ns
ns
pF
pF
Semiconductor High−Speed CMOS Data Book (DL129/D)
Typical @ 25°C, V_CC = 5.0 V
C_PD Power Dissipation Capacitance (Per Flip−Flop)*
65
pF
* Used to determine the no−load dynamic power consumption: P_D = C_PD V_CC2f + I_CC V_CC. For load considerations, see Chapter 2 of the
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (V_CC = 5.0 V ± 10%, Input t_r = t_f = 6.0 ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
Parameter
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tsu Minimum Setup Time, Data to Clock
(Figure 3)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _th
Minimum Hold Time, Clock to Data
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{(Figure 3)}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tw
Minimum Pulse Width, Clock
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (Figure 1)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ t_r, t_f Maximum Input Rise and Fall Times
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{(Figure 1)}
Guaranteed Limit
– 55 to 25_C v 85_C v 125_C Unit
12
15
18
ns
5.0
5.0
5.0
ns
12
15
18
ns
500
500
500
ns
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