MC74HC589A_14 Datasheet, PDF (4/12 Pages) ON Semiconductor – 8-Bit Serial or Parallel-Input/Serial-Output Shift Register with 3-State Output

MC74HC589A
AC ELECTRICAL CHARACTERISTICS (C_L = 50 pF, Input t_r = t_f = 6 ns)
Symbol
Parameter
f_max Maximum Clock Frequency (50% Duty Cycle)
(Figures 3 and9)
t_PLH,
t_PHL
Maximum Propagation Delay, Latch Clock to Q_H
(Figures 2 and 9)
t_PLH,
t_PHL
Maximum Propagation Delay, Shift Clock to Q_H
(Figures 3 and 9)
t_PLH,
t_PHL
Maximum Propagation Delay, Serial Shift/Parallel Load to Q_H
(Figures 5 and 9)
t_PLZ,
t_PHZ
Maximum Propagation Delay, Output Enable to Q_H
(Figures 4 and 10)
t_PZL,
t_PZH
Maximum Propagation Delay, Output Enable to Q_H
(Figures 4 and 10)
t_TLH,
t_THL
Maximum Output Transition Time, Any Output
(Figures 2 and 9)
C_in Maximum Input Capacitance
C_out Maximum Three−State Output Capacitance
(Output in High−Impedance State)
V_CC
Guaranteed Limit
V −55_C to 25_C ≤ 85_C ≤ 125_C Unit
2.0
6.0
3.0
15
4.5
30
6.0
35
4.8
4.0
MHz
10
8.0
24
20
28
24
2.0
175
3.0
100
4.5
40
6.0
30
225
275
ns
110
125
50
60
40
50
2.0
160
3.0
90
4.5
30
6.0
25
200
240
ns
130
160
40
48
30
40
2.0
160
3.0
90
4.5
30
6.0
25
200
240
ns
130
160
40
48
30
40
2.0
150
3.0
80
4.5
27
6.0
23
170
200
ns
100
130
30
40
25
30
2.0
150
3.0
80
4.5
27
6.0
23
170
200
ns
100
130
30
40
25
30
2.0
60
3.0
23
4.5
12
6.0
10
75
90
ns
27
31
15
18
13
15
−
10
10
10
pF
−
15
15
15
pF
Typical @ 25_C, V_CC = 5.0 V
C_PD Power Dissipation Capacitance (per Package)*
50
pF
*Used to determine the no−load dynamic power consumption: P_D = C_PD V_CC2f + I_CC V_CC.
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