MC74HC4040A_14 Datasheet, PDF (4/8 Pages) ON Semiconductor – 12-Stage Binary Ripple Counter

MC74HC4040A
PIN DESCRIPTIONS
INPUTS
Clock (Pin 10)
Negative−edge triggering clock input. A high−to−low
transition on this input advances the state of the counter.
Reset (Pin 11)
Active−high reset. A high level applied to this input
asynchronously resets the counter to its zero state, thus
forcing all Q outputs low.
OUTPUTS
Q1 thru Q12 (Pins 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1)
Active−high outputs. Each Qn output divides the Clock
input frequency by 2^N.
SWITCHING WAVEFORMS
t_f
t_r
90%
V_CC
Clock
50%
10%
GND
t_w
1/f_MAX
t_PLH
t_PHL
90%
Q1 _50%
10%
t_TLH
t_THL
Clock
Reset
Any Q
V_CC
50%
GND
t_rec
t_w
V_CC
50%
GND
t_PHL
50%
Figure 2.
Figure 3.
Qn
50%
t_PLH
V_CC
GND
t_PHL
Qn+1
50%
Figure 4.
DEVICE
UNDER
TEST
TEST
POINT
OUTPUT
C_L*
*Includes all probe and jig capacitance
Figure 5. Test Circuit
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