MC74HC240A_14 Datasheet, PDF (4/7 Pages) ON Semiconductor – Octal 3-State Inverting Buffer/Line Driver/Line Receiver

DATA INPUT
A OR B
t_PHL
OUTPUT
YA OR YB
t_THL
t_r
90%
50%
10%
90%
50%
10%
Figure 1.
MC74HC240A
SWITCHING WAVEFORMS
t_f
V_CC
GND
t_PLH
t_TLH
ENABLE
OUTPUT Y
OUTPUT Y
50%
t_PZL
t_PLZ
50%
t_PZH
t_PHZ
50%
Figure 2.
V_CC
GND
HIGH
IMPEDANCE
10% V_OL
90% VOH
HIGH
IMPEDANCE
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
C_L*
*Includes all probe and jig capacitance
Figure 3. Test Circuit
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 kW
C_L*
CONNECT TO V_CC WHEN
TESTING t_PLZ AND t_PZL.
CONNECT TO GND WHEN
TESTING t_PHZ AND t_PZH.
*Includes all probe and jig capacitance
Figure 4. Test Circuit
PIN DESCRIPTIONS
INPUTS
A1, A2, A3, A4, B1, B2, B3, B4
(Pins 2, 4, 6, 8, 11, 13, 15, 17)
Data input pins. Data on these pins appear in inverted form
on the corresponding Y outputs, when the outputs are
enabled.
CONTROLS
Enable A, Enable B (Pins 1, 19)
Output enables (active−low). When a low level is applied
to these pins, the outputs are enabled and the devices
function as inverters. When a high level is applied, the
outputs assume the high−impedance state.
OUTPUTS
YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4
(Pins 18, 16, 14, 12, 9, 7, 5, 3)
Device outputs. Depending upon the state of the
output−enable pins, these outputs are either inverting
outputs or high−impedance outputs.
http://onsemi.com
4