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MC14532B Datasheet, PDF (4/12 Pages) Motorola, Inc – 8-BIT PRIORITY ENCODER
MC14532B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Characteristic
Symbol
VDD
Min
Typ (8.)
Max
Unit
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
ns
tTHL
5.0
—
100
200
10
—
50
100
15
—
40
80
Propagation Delay Time — Ein to Eout
tPLH, tPHL = (1.7 ns/pF) CL + 120 ns
tPLH, tPHL = (0.66 ns/pF) CL + 77 ns
tPLH, tPHL = (0.5 ns/pF) CL + 55 ns
tPLH,
ns
tPHL
5.0
—
205
410
10
—
110
220
15
—
80
160
Propagation Delay Time — Ein to GS
tPLH, tPHL = (1.7 ns/pF) CL + 90 ns
tPLH, tPHL = (0.66 ns/pF) CL 57 ns
tPLH, tPHL = (0.5 ns/pF) CL + 40 ns
tPLH,
ns
tPHL
5.0
—
175
350
10
—
90
180
15
—
65
130
Propagation Delay Time — Ein to Qn
tPLH, tPHL = (1.7 ns/pF) CL + 195 ns
tPLH, tPHL = (0.66 ns/pF) CL + 107 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
tPHL,
ns
tPLH
5.0
—
280
560
10
—
140
280
15
—
100
200
Propagation Delay Time — Dn to Qn
tPLH, tPHL = (1.7 ns/pF) CL + 265 ns
tPLH, tPHL = (0.66 ns/pF) CL + 137 ns
tPLH, tPHL = (0.5 ns/pF) CL + 85 ns
tPLH,
ns
tPHL
5.0
—
300
600
10
—
170
340
15
—
110
220
Propagation Delay Time — Dn to GS
tPLH, tPHL = (1.7 ns/pF) CL + 195 ns
tPLH, tPHL = (0.66 ns/pF) CL + 107 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
tPLH,
ns
tPHL
5.0
—
280
560
10
—
140
280
15
—
100
200
7. The formulas given are for the typical characteristics only at 25_C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
SWITCH
MATRIX
Ein
D0
D1
Eout
D2
Q0
D3
Q1
D4
Q2
D5
GS
D6
D7
Vout
ID
EXTERNAL
POWER
SUPPLY
Output
Under
Test
Eout
Q0
Q1
Q2
GS
VGS = VDD
VDS = Vout
Sink Current
D0 thru D7 Ein
X
0
X
0
X
0
X
0
X
0
VGS = – VDD
VDS = Vout – VDD
Source Current
D0 thru D6 D7 Ein
0
01
0
11
0
11
0
11
0
11
Figure 1. Typical Sink and Source
Current Characteristics
500 µF
PULSE
GENERATOR
(fo)
VDD
ID
0.01 µF
Ein
Eout
D0
CL
D1
Q0
D2
CL
D3
Q1
D4
CL
D5
Q2
D6
CL
D7
GS
VSS
CL
Figure 2. Typical Power Dissipation Test Circuit
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