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MC14503B Datasheet, PDF (4/8 Pages) ON Semiconductor – Hex Non-Inverting 3-State Buffer | |||
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MC14503B
SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C)
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ Characteristic
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ Output Rise Time
tTLH = (0.5 ns/pF) CL + 20 ns
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ tTLH = (0.3 ns/pF) CL + 8.0 ns
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ tTLH = (0.2 ns/pF) CL + 8.0 ns
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ Output Fall Time
tTHL = (0.5 ns/pF) CL + 20 ns
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ tTHL = (0.3 ns/pF) CL + 8.0 ns
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ tTHL = (0.2 ns/pF) CL + 8.0 ns
TurnâOff Delay Time, all Outputs
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ tPLH = (0.3 ns/pF) CL + 60 ns
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ tPLH = (0.15 ns/pF) CL + 27 ns
tPLH = (0.1 ns/pF) CL + 20 ns
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ TurnâOn Delay Time, all Outputs
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ tPHL = (0.3 ns/pF) CL + 60 ns
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ tPHL = (0.15 ns/pF) CL + 27 ns
tPHL = (0.1 ns/pF) CL + 20 ns
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ 3âState Propagation Delay Time
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ Output â1â to High Impedance
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ Output â0â to High Impedance
Symbol
tTLH
tTHL
tPLH
tPHL
tPHZ
tPLZ
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ High Impedance to â1â Level
tPZH
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ High Impedance to â0â Level
tPZL
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ 7. Theformulasgivenareforthetypicalcharacteristicsonlyat25_C.
VDD
All Types
VCC
Typ (8.)
Max
5.0
45
90
10
23
45
15
18
35
Unit
ns
ns
5.0
45
90
10
23
45
15
18
35
ns
5.0
75
150
10
35
70
15
25
50
ns
5.0
75
150
10
35
70
15
25
50
5.0
75
150
ns
10
40
80
15
35
70
5.0
80
160
ns
10
40
80
15
35
70
5.0
65
130
ns
10
25
50
15
20
40
5.0
100
200
ns
10
35
70
15
25
50
8. Data labelled âTypâ is not to be used for design purposes but is intended as an indication of the ICâs potential performance.
DISABLE
INPUT
PULSE
GENERATOR
VDD
16
INPUT
VSS
OUTPUT
CL
20 ns
INPUT
tPLH
OUTPUT
tPLH
90%
90%
tTLH
20 ns
VDD
50%
10% VSS
tPHL
VOH
50%
10% VOL
tTHL
tPHL
Figure 1. Switching Time Test Circuit and Waveforms
(tTLH, tTHL, tPHL, and tPLH)
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