MC14012B_11 Datasheet, PDF (4/8 Pages) ON Semiconductor – Dual 4-Input NAND Gates

MC14012B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS (Note 5⁾ (C_L = 50 pF, T_A = 25_C)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Characteristic
Symbol
V_DD
Vdc
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Output Rise Time}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{tTLH = (1.35 ns/pF) CL + 33 ns}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ t_TLH = (0.60 ns/pF) C_L + 20 ns
t_TLH = (0.40 ns/PF) C_L + 20 ns
t_TLH
5.0
10
15
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Output Fall Time}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{tTHL = (1.35 ns/pF) CL + 33 ns}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{tTHL = (0.60 ns/pF) CL + 20 ns}
t_THL = (0.40 ns/pF) C_L + 20 ns
t_THL
5.0
10
15
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Propagation Delay Time
t_PLH, t_PHL = (0.90 ns/pF) C_L + 115 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{tPLH, tPHL = (0.36 ns/pF) CL + 47 ns}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^tPLH^{, t}PHL ^{= (0.26 ns/pF) C}L ^{+ 37 ns}
t_PLH, t_PHL
5.0
10
15
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{5. The formulas given are for the typical characteristics only at 25_C.}
Min
Typ
Max
Unit
(Note 6)
ns
−
100
200
−
50
100
−
40
80
ns
−
100
200
−
50
100
−
40
80
ns
−
160
300
−
65
130
−
50
100
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
14 V_DD
PULSE
GENERATOR
INPUT
OUTPUT
20 ns
20 ns
INPUT
90%
50%
V_DD
10%
0V
t_PHL
t_PLH
*
C_L
OUTPUT
INVERTING _tTHL
90%
50%
10%
t_TLH
V_OH
V_OL
7 V_SS
OUTPUT ^tPLH
t_PHL
90%
V_OH
NON−INVERTING
50%
*All unused inputs of AND, NAND gates must be connected to V_DD.
All unused inputs of OR, NOR gates must be connected to V_SS.
10%
V_OL
t_TLH
t_THL
Figure 3. Switching Time Test Circuit and Waveforms
V_DD
2, 9
3, 10
V_SS
4, 11
SAME AS
5, 12
ABOVE
14 V_DD
*
1, 13
*Inverter omitted
7 V_SS
Figure 4. Circuit Schematic − One of Two Gates Shown
http://onsemi.com
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