ASM1832 Datasheet, PDF (4/9 Pages) Alliance Semiconductor Corporation – 3.3V UP Power Supply Monitor and Reset Circuit

ASM1832
Detailed Description
The ASM1832 monitors the microprocessor or
microcontroller power supply and issues reset signals, both
active HIGH and active LOW, that halt processor operation
whenever the power supply voltage levels are outside a
predetermined tolerance.
RESET and RESET Outputs
RESET and RESET signals are active for a minimum of
250 ms after the supply has returned to in−tolerance level.
This allows the power supply and monitored processor to
stabilize before instruction execution is allowed to begin.
Trip Point Tolerance Selection
The TOL input is used to determine the level V_CC can vary
below 3.3 V without asserting a reset. With TOL connected
to V_CC, RESET and RESET become active whenever V_CC
falls below 2.64 V. RESET and RESET become active when
the V_CC falls below 2.98 V if TOL is connected to ground.
After V_CC has risen above the trip point set by TOL,
RESET and RESET remain active for a minimum time
period of 250 ms. On power−down, once V_CC falls below
the reset threshold RESET stays LOW and is guaranteed to
be 0.4 V or less until V_CC drops below 1.2 V. The reset
output on the ASM1832 uses a push−pull drive stage that can
maintain a valid output below 1.2 V. To sink current with
V_CC below 1.2 V, a resistor can be connected from the reset
pin (RESET) to Ground. This configuration will give a valid
value on the reset output with V_CC approaching 0 V. During
both power up and down, the configuration will draw current
when the RESET is in the high state. The value of 100 KW
should be adequate to maintain a valid condition. The active
HIGH reset signal is valid down to a V_CC level of 1.2 V also.
Table 4.
Tolerance
Select
TOL = V_CC
TOL = GND
Tolerance
20%
10%
TRIP Point Voltage (V)
Min Nom Max
2.47 2.55 2.64
2.80 2.88 2.97
Figure 3.
Figure 4. Timing Diagram: Power Up
Application Information
Manual Reset Operation
Push−button switch input, PBRST, allows the user to
override the internal trip point detection circuits and issue
reset signals. The pushbutton input is debounced and is
pulled HIGH through an internal 40 kW resistor.
Figure 5. Timing Diagram: Power Down
When PBRST is held LOW for the minimum time t_PB,
both resets become active and remain active for a minimum
time period of 250 ms after PBRST returns HIGH.
The debounced input is guaranteed to recognize pulses
greater than 20 ms. No external pull−up resistor is required,
since PBRST is pulled HIGH by an internal 40 kW resistor.
The PBRST can be driven from a TTL or CMOS logic line
or shorted to ground with a mechanical switch.
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