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74HC86 Datasheet, PDF (4/8 Pages) NXP Semiconductors – Quad 2-input EXCLUSIVE-OR gate
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74HC86
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
– 55 to
(V)
25_C v 85_C v 125_C Unit
VIH Minimum High−Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA
2.0
1.5
1.5
1.5
V
3.0
2.1
2.1
2.1
4.5
3.15
3.15
3.15
6.0
4.2
4.2
4.2
VIL Maximum Low−Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA
2.0
0.5
0.5
0.5
V
3.0
0.9
0.9
0.9
4.5
1.35
1.35
1.35
6.0
1.8
1.8
1.8
VOH Minimum High−Level Output
Voltage
Vin = VIH or VIL
|Iout| v 20 mA
2.0
1.9
1.9
1.9
V
4.5
4.4
4.4
4.4
6.0
5.9
5.9
5.9
Vin = VIH or VIL |Iout| v 2.4 mA 3.0
|Iout| v 4.0 mA 4.5
|Iout| v 5.2 mA 6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
VOL Maximum Low−Level Output
Voltage
Vin = VIH or VIL
|Iout| v 20 mA
2.0
0.1
0.1
0.1
V
4.5
0.1
0.1
0.1
6.0
0.1
0.1
0.1
Vin = VIH or VIL |Iout| v 2.4 mA 3.0
|Iout| v 4.0 mA 4.5
|Iout| v 5.2 mA 6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
Iin
Maximum Input Leakage Current Vin = VCC or GND
6.0
±0.1
±1.0
±1.0
mA
ICC Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 mA
6.0
2.0
20
40
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book
(DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input t, = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
VCC
– 55 to
(V)
25_C v 85_C v 125_C Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
2.0
100
125
150
ns
3.0
80
90
110
4.5
20
25
31
6.0
17
21
26
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
75
3.0
30
4.5
15
6.0
13
95
110
ns
40
55
19
22
16
19
Cin Maximum Input Capacitance
—
10
10
10
pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD Power Dissipation Capacitance (Per Gate)*
33
pF
* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
http://onsemi.com
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