FS6131_08 Datasheet, PDF (37/44 Pages) ON Semiconductor – Programmable Line Lock Clock Generator IC

FS6131
Next, express the output and input frequencies as a ratio of fCLK to fREF, where fCLK has also been converted to a product of prime numbers.
f _{CLK =} 100000000.00 ₌
( ) 2⁸ × 5⁸
f _REF
14318181.81
⎜⎜⎝⎛
2⁵
×
3^{2 ×}
11
5⁷
×
7¹
⎟⎟⎠⎞
Simplifying the above equation yields
( ) f_{CLK =} 2³ × 5¹ ×11
( ) f _REF
3² × 7
Deciding how to apportion the denominator integers between the reference divider and the post divider is an iterative process. To
obtain the best performance, the VCO should be operated at the highest frequency possible without exceeding its upper limit of
230MHz. (see Table 15). The VCO frequency (fVCO) can be calculated by
f _VCO
=
f _REF
×
N_F
N_R
Recall that the reference divider can have a value between 1 and 4096, but the post divider is limited to values derived from
N _Px = N _P1 × N _P2 × N _P3
where the values NP1, NP2 and NP3 are found in Table 8.
In this example, the smallest integer that can be removed from the denominator of Eqn. 2 is three. Set the post divider at NPx=3, and the
ratio of fCLK to fREF becomes (from Eqn. 1)
( ) f _CLK
f _REF
=
2³ × 5¹ ×11
(3× 7)
×
1
3
Unfortunately, a post divider modulus of three requires a VCO frequency of 300MHz, which is greater than the allowable fVCO noted in
Table 15. For the best PLL performance, program the post divider modulus to allow the VCO to operate at a nominal frequency that is
at least 70MHz but less then 230MHz. Therefore, the reference divider cannot be reduced below the modulus of 32´7 (or 63) as shown
in Eqn. 2.
However, the VCO can still be operated at a frequency higher than fCLK. Multiplying both the numerator and the denominator by two
does not alter the output frequency, but it does increase the VCO frequency.
( ) f_{CLK =} N _{F ×} 1 ₌ 2³ × 5¹ ×11 × 2 _× 1 ₌ 880 _× 1
( ) f _REF N _R N _Px
3² × 7
2 63 2
As Eqn. 3 shows, the VCO frequency can be doubled by multiplying the feedback divider by two. Set the post divider to two to return
the output frequency to the desired modulus. These divider settings place the VCO frequency at 200MHz.
12.2 Example Programming
To generate 100.000MHz from 14.318MHz, program the following (refer to Figure 24):
• Set the reference divider input to select the VCXO via REFDSRC=0
• Set the PFD input to select the reference divider and the feedback divider via PDREF=0 and PDFBK=0
• Set the reference divider (NR) to a modulus of 63 via REFDIV[11:0]
• Set the feedback divider input to select the VCO via FBKDSRC=1
• Set the feedback divider (NF) to a modulus of 880 via FBKDIV[14:0]
• Set NP1=2, NP2=1 and NP3=1 for a combined post divider modulus of NPx=2 via POST1[1:0], POST2[1:0] and POST3[1:0].
• Select the internal loop filter via EXTLF=0
• Set XLVTEN=0 and XLPDEN=1 to disable the VCXO fine tune and the crystal loop phase frequency detector
• Set VCOSPD=0 to select the VCO high speed range
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