NCP5331 Datasheet, PDF (33/38 Pages) ON Semiconductor – Two-Phase PWM Controller with Integrated Gate Drivers

NCP5331
First, use Equation 15 to calculate the voltage across the
output inductor due to the 52 A load current being shared
equally between the two phases.
DVLo + VIN * VCORE,NO- _LOAD
(15)
) (IO,MAXń2) @ ESROUTńNOUT
+ 12 V * 1.575 V ) 52 Ań2 @ 19 mWń6
+ 10.51 V
Second, use Equation 16 to determine the rate of current
increase in the output inductor when the load is applied (i.e.,
Lo has decreased to 88% due to the dc current).
dILońdt + DVLońLo
(16)
+ 10.51 Vń729 nH + 14.4 Vńms
Finally, use Equation 17 and Equation 18 to calculate the
minimum input inductance value.
DVCi ^{+ ESRINńNIN @ dILońdt @ DńfSW}
(17)
+ 13 mWń5 @ 14.4 Vńms @ 0.146ń200 kHz
+ 28 mV
LiMIN + DVCi ń dIINńdtMAX
(18)
+ 28 mVń0.50 Ańms + 55 nH
Next, choose the small, cost effective T30-26 core from
Micrometals (33.5 nH/N²) with #16 AWG. The design
requires only 1.28 turns to achieve the minimum inductance
value. We allow for inductance “swing” at full-load by
using three turns. The input inductor’s value will be
Li + 32 @ 33.5 nHńN2 + 301 nH
This inductor is available as part number CTX15-14771
from Coiltronics.
5. MOSFET & Heatsink Selection
For the upper MOSFET we choose two (1) NTD60N03
and for the lower MOSFETs we choose two (2) NTD80N02,
both are from ON Semiconductor. The following parameters
are derived from the data sheets.
NCP5331 Parameter
Gate Drive Current
Upper Gate Voltage
Lower Gate Voltage
Gate Nonoverlap Time
Value
1.5 A for 1.0 µs
6.5 V
11.5 V
65 ns
Parameter
R_DS(on)
Q_SWITCH
Q_RR
Q_OSS
V_F,diode
θ_JC
NTD60N03
8.0 mΩ @ 6.5 V
27 nC
43 nC
12 nC
0.75 V @ 2.3 A
1.65°C/W
NTD80N02
5.0 mΩ @ 10 V
26 nC
36 nC
12 nC
0.92 V @ 20 A
1.65°C/W
The rms value of the current in the control MOSFET is
calculated from Equation 20 and the previously derived
values for D, I_LMAX, and I_LMIN at the converter’s maximum
output current.
IRMS,CNTL + [D @ (ILo,MAX2 ) ILo,MAX @ ILo,MIN ⁽²⁰⁾
) ILo,MIN2)ń3]1^ń2
+ 0.097 @ [(29.62 ) 29.6 @ 22.4 ) 22.42)ń3]1^ń2
+ 2.53 ARMS
Equation 19 is used to calculate the power dissipation of
the control MOSFET but has been modified for one upper
and two lower MOSFETs.
PD,CONTROL + {(IRMS,CNTL2) @ RDS(on)}
(19)
) (ILo,MAX @ QswitchńIg @ VIN @ fSW)
) (3 @ Qossń2 @ VIN @ fSW) ) (VIN @ QRR @ fSW)
+ {2.532 ARMS @ 8.0 mW}
) (29.6 A @ 27 nCń1.5 A @ 12 V @ 200 kHz)
) (3 @ 12 nCń2 @ 12 V @ 200 kHz)
) (12 V @ 43 nC @ 200 kHz)
+ 0.051 W ) 1.28 W ) 0.043 W ) 0.10 W
+ 1.48 W per FET
The rms value of the current in the synchronous MOSFET
is calculated from Equation 27 and the previously derived
values for D, I_Lo,MAX, and I_Lo,MIN at the converter’s
maximum output current.
IRMS,SYNCH + [(1 * D) @
(27)
(ILo,MAX2 ) ILo,MAX @ ILo,MIN ) ILo,MIN2)ń3]1^ń2
+ (1 * 0.097) @ [(29.62 ) 29.6 @ 22.4 ) 22.42)ń3]1^ń2
+ 23.5 ARMS (shared by two synchronous MOSFETs)
Equation 26 is used to calculate the power dissipation of
each synchronous MOSFET. Note: The rms current is
shared by the two lower MOSFETs so the total rms current
is divided by two in the following equation. Also, during the
nonoverlap time, the per-phase current is shared by two
body diodes so the full load current is divided between two
phases and two forward body diodes per phase.
PD,SYNCH + (IRMS,SYNCH2 @ RDS(on))
(26)
) (Vfdiode @ IO,MAXń2 @ t_nonoverlap @ fSW)
+ ^NJ(23.5ń2)2 ARMS @ 5.0 mW^Nj
) ^NJ0.92 V @ (52 Ań2ń2) @ 65 ns @ 200 kHz^Nj
+ 0.69 W ) 0.16 W + 0.85 W per FET
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