NCP6151A Datasheet, PDF (32/34 Pages) ON Semiconductor – Dual Output 4 Phase +1/0 Phase Controller

enables and sets the PWM signal to the 2.0V MID state to indicate that the drivers should be in diode mode.
DRVON will then be asserted and the COMP pin released to begin soft-start. The DAC will ramp from Zero to
the target DAC codes and the PWM outputs will begin to fire. Each phase will move out of the MID state when
the first PWM pulse is produced preventing the discharge of a pre-charged output.
Soft-Start Sequence
Over Current Latch- Off Protection
The NCP6151/NCP6151A provides two different types of current limit protection. During normal operation a
programmable total current limit is provided that scales with the phase count during power saving operation.
This limit is proprammed with a resistor between the CSCOMP and ILIM pins. A second fixed per-phase current
limit is provided for safe-start up monitoring during soft-start. The level of total current limit is set with the
resistor from the ILIM pin to CSCOMP. The current through the external resistor connected between ILIM and
CSCOMP is then compared to the internal current of 10uA and 15uA. If the current into the ILIM pin exceeds the
10A level an internal latch-off counter starts. The controller shuts down if the fault is not removed after 50us. If
the current into the pin exceeds 15uA the controller will shut down immediately. To recover from an OCP fault
the EN pin must be cycled low.
The over-current limit is programmed by a resistor on the ILIM pin. The resistor value can be calculated by the
following equation:
R_ILIM
= ^{VCSCOMP − VCSREF}
10uA
Under Voltage Monitor
The output voltage is monitored at the output of the differential amplifier for UVLO. If the output falls more than
300mV below the DAC-DROOP voltage the UVLO comparator will trip sending the VR_RDY signal low.
Over Voltage Protection
During normal operation the output voltage is monitored at the differential inputs VSP and VSN. If the output
voltage exceeds the DAC voltage by approximately 175 mV, PWMs will be forced low until the voltage drops
below the OVP threshold after the first OVP trip the DAC will ramp down to zero to avoid a negative output
voltage spike during shutdown. When the DAC gets to zero the PWMs will be forced low and the DRVON will
remain high. To reset the part the Enable pin must be cycled low. During soft-start, the OVP threshold is set to
Rev1, 032012
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