KAI-08670 Datasheet, PDF (31/52 Pages) ON Semiconductor – INTERLINE CCD IMAGE SENSOR

KAI−08670
Pixel Timing
This timing is for transferring one pixel from the HCCD to the output amplifier.
Table 21. PIXEL TIMING
Full Resolution, High Gain or Low Gain
1/4 Resolution, High Gain or Low Gain
1/4 Resolution XLDR
Device
Pin
V1T
Quad
Dual
VOUTa
VOUTc
Dual
VOUTa
VOUTb
−8 V
Single
VOUTa
Quad
Dual
VOUTa
VOUTc
Dual
VOUTa
VOUTb
−8 V
Single
VOUTa
Quad
Dual
VOUTa
VOUTc
Dual
VOUTa
VOUTb
−8 V
Single
VOUTa
V2T
−8 V
−8 V
−8 V
V3T
0V
0V
0V
V4T
0V
0V
0V
V1B
−8 V
−8 V
−8 V
V2B
0V
0V
0V
V3B
0V
0V
0V
V4B
−8 V
−8 V
−8 V
H1Sa
P1
P1Q
P1XL
H1Ba
P1
P1Q
P1XL
H2Sa
P2
P2Q
P2XL
H2Ba
P2
P2Q
P2XL
Ra
RHG/RLG
RHGQ/RLGQ
RXL
H1Sb
P1
P1Q
P1XL
H1Bb
P1
P2
P1
P2
P1Q
P2Q
P1Q
P2Q
P1XL
P2XL
P1XL
P2XL
H2Sb
P2
P2Q
P2XL
H2Bb
P2
P1
P2
P1
P2Q
P1Q
P2Q
P1Q
P2XL
P1XL
P2XL
P1XL
Rb
RHG/ (Note 1) RHG/ (Note 1) RHGQ/ (Note 1) RHGQ/ (Note 1)
RXL
(Note 1)
RXL
(Note 1)
RLG
RLG
RLGQ
RLGQ
R2ab
R2HG/R2LG
R2HGQ/R2LGQ
R2XL
FDGab
−8 V
−8 V
−8 V
H1Sc
P1
(Note 1)
P1Q
(Note 1)
P1XL
(Note 1)
H1Bc
P1
(Note 1)
P1Q
(Note 1)
P1XL
(Note 1)
H2Sc
P2
(Note 1)
P2Q
(Note 1)
P2XL
(Note 1)
H2Bc
P2
(Note 1)
P2Q
(Note 1)
P2XL
(Note 1)
Rc
RHG/RLG
(Note 1)
RHGQ/RLGQ
(Note 1)
RXL
(Note 1)
H1Sd
P1
(Note 1)
P1Q
(Note 1)
P1XL
(Note 1)
H1Bd
P1
P2
(Note 1)
P1Q
P2Q
(Note 1)
P1XL
P2XL
(Note 1)
H2Sd
P2
(Note 1)
P2Q
(Note 1)
P2XL
(Note 1)
H2Bd
P2
P1
(Note 1)
P2Q
P1Q
(Note 1)
P2XL
P1XL
(Note 1)
Rd
RHG/ (Note 1)
RLG
(Note 1)
RHGQ/ (Note 1)
RLGQ
(Note 1)
RXL
(Note 1)
(Note 1)
R2cd
R2HG/R2LG
(Note 1)
R2HGQ/R2LGQ
(Note 1)
R2XL
(Note 1)
FDGcd
−8 V
−8 V
−8 V
SHP
(Note 2)
SHP1
SHPQ
(Note 4)
SHD
(Note 2)
SHD1
SHDQ
(Note 5)
1. This clock should be held at its high level voltage (0 V) or held at +5.0 V for compatibility with TRUESENSE 5.5 micron Interline Transfer
CCD family of products.
2. SHP and SHD are the sample clocks for the analog front end (AFE) signal processor.
3. This note intentionally left empty.
4. Use SHPLG for the AFE processing the low gain signal. Use SHPHG for the AFE processing the high gain signal.
5. Use SHDLG for the AFE processing the low gain signal. Use SHDHG for the AFE processing the high gain signal.
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