SN74LS175 Datasheet, PDF (3/8 Pages) ON Semiconductor – LOW POWER SCHOTTKY

SN74LS175
FUNCTIONAL DESCRIPTION
The LS175 consists of four edge-triggered D flip-flops
with individual D inputs and Q and Q outputs. The Clock and
Master Reset are common. The four flip-flops will store the
state of their individual D inputs on the LOW to HIGH Clock
(CP) transition, causing individual Q and Q outputs to
follow. A LOW input on the Master Reset (MR) will force
all Q outputs LOW and Q outputs HIGH independent of
Clock or Data inputs.
The LS175 is useful for general logic applications where
a common Master Reset and Clock are acceptable.
TRUTH TABLE
Inputs (t = n, MR = H)
Outputs (t = n+1) Note 1
D
Q
Q
L
L
H
H
H
L
Note 1: t = n + 1 indicates conditions after next clock.
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
V_IH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
V_IL
Input LOW Voltage
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
V_IK
Input Clamp Diode Voltage
– 0.65 – 1.5
V
V_CC = MIN, I_IN = – 18 mA
V_OH
Output HIGH Voltage
2.7
3.5
V
V_CC = MIN, I_OH = MAX, V_IN = V_IH
or V_IL per Truth Table
V_OL
Output LOW Voltage
0.25 0.4
0.35 0.5
V
I_OL = 4.0 mA
V
I_OL = 8.0 mA
V_CC = V_CC MIN,
V_IN = V_IL or V_IH
per Truth Table
I_IH
Input HIGH Current
20
µA V_CC = MAX, V_IN = 2.7 V
0.1
mA V_CC = MAX, V_IN = 7.0 V
I_IL
Input LOW Current
– 0.4 mA V_CC = MAX, V_IN = 0.4 V
I_OS
Short Circuit Current (Note 1)
– 20
– 100 mA V_CC = MAX
I_CC
Power Supply Current
18
mA V_CC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
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