SN74LS165 Datasheet, PDF (3/8 Pages) ON Semiconductor – LOW POWER SCHOTTKY

10 D_S
2 CP1
15 CP₂
1 PL
V_CC = PIN 16
GND = PIN 8
= PIN NUMBERS
SN74LS165
LOGIC DIAGRAM
11
12
13
14
3
4
5
6
P₀
P₁
P₂
P₃
P₄
P₅
P₆
P₇
PRESET
S Q₀
CP
R _CLQ₀
PRESET
S Q₁
CP
R _CLQ₁
PRESET
S Q₂
CP
R _CL^Q2
PRESET
S Q₃
CP
R _CLQ₃
PRESET
S Q₄
CP
R _CLQ₄
PRESET
S Q₅
CP
R _CLQ₅
PRESET
S Q₆
CP
R _CLQ₆
PRESET
S Q₇
9
CP
R _CL Q₇
7
FUNCTIONAL DESCRIPTION
The SN74LS165 contains eight clocked master/slave RS
flip-flops connected as a shift register, with auxiliary gating
to provide overriding asynchronous parallel entry. Parallel
data enters when the PL signal is LOW. The parallel data can
change while PL is LOW, provided that the recommended
setup and hold times are observed.
For clock operation, PL must be HIGH. The two clock
inputs perform identically; one can be used as a clock inhibit
by applying a HIGH signal. To avoid double clocking,
however, the inhibit signal should only go HIGH while the
clock is HIGH. Otherwise, the rising inhibit signal will cause
the same response as a rising clock edge. The flip-flops are
edge-triggered for serial operations. The serial input data
can change at any time, provided only that the recommended
setup and hold times are observed, with respect to the rising
edge of the clock.
CP
PL
1 2 Q₀ Q₁
L X X P₀ P₁
HL
D_S Q₀
HH
Q₀ Q₁
H
L D_S Q₀
H
H Q₀ Q₁
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
TRUTH TABLE
CONTENTS
Q₂ Q₃ Q₄ Q₅
P₂ P₃ P₄ P₅
Q₁ Q₂ Q₃ Q₄
Q₂ Q₃ Q₄ Q₅
Q₁ Q₂ Q₃ Q₄
Q₂ Q₃ Q₄ Q₅
Q₆ Q₇
P₆ P₇
Q₅ Q₆
Q₆ Q₇
Q₅ Q₆
Q₆ Q₇
RESPONSE
Parallel Entry
Right Shift
No Change
Right Shift
No Change
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