NCP59749 Datasheet, PDF (3/10 Pages) ON Semiconductor – 3.0 A, Dual-Rail Very Low‐Dropout Linear Regulator with Programmable Soft‐Start

NCP59749
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Input Voltage Range
Input Voltage Range
Enable Voltage Range
Power-Good Voltage Range
PG Sink Current
SS Pin Voltage Range
Feedback Pin Voltage Range
Output Voltage Range
Maximum Output Current
Output Short Circuit Duration
V_IN
−0.3 to +6
V
V_BIAS
−0.3 to +6
V
V_EN
−0.3 to +6
V
V_PG
−0.3 to +6
V
I_PG
0 to +1.5
mA
V_SS
−0.3 to +6
V
V_FB
−0.3 to +6
V
V_OUT
−0.3 to (V_IN + 0.3) ≤ 6
V
I_OUT
Internally Limited
Indefinite
Continuous Total Power Dissipation
P_D
See Thermal Characteristics Table and Formula
Maximum Junction Temperature
T_JMAX
+125
°C
Storage Junction Temperature Range
T_STG
−55 to +150
°C
ESD Capability, Human Body Model (Note 2)
ESD_HBM
2000
V
ESD Capability, Machine Model (Note 2)
ESD_MM
200
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per EIA/JESD22-A114
ESD Machine Model tested per EIA/JESD22-A115
Latch-up Current Maximum Rating tested per JEDEC standard: JESD78.
Table 3. THERMAL CHARACTERISTICS
Rating
Symbol
Value
Unit
Thermal Characteristics, QFN20, 5x5, 0.65P package
Thermal Resistance, Junction−to−Ambient (Note 5)
R_qJA
30.5
°C/W
Thermal Resistance, Junction−to−Case (bottom) (Note 6)
R_qJC
4.1
°C/W
3. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
4. Thermal data are derived by thermal simulations based on methodology specified in the JEDEC JESD51 series standards. The following
assumptions are used in the simulations:
− This data was generated with only a single device at the center of a high−K (2s2p) board with 3 in x 3 in copper area which follows the
− JEDEC51.7 guidelines.
− The exposed pad is connected to the PCB ground layer through a 4x4 thermal via array. Vias are 0.3 mm diameter, plated.
− Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.
5. The junction−to−ambient thermal resistance under natural convection is obtained in a simulation on a high−K board, following the JEDEC51.7
guidelines with assumptions as above, in an environment described in JESD51−2a.
6. The junction−to−case (bottom) thermal resistance is obtained by simulating a cold plate test on the IC exposed pad. Test description can
be found in the ANSI SEMI standard G30−88.
Table 4. RECOMMENDED OPERATING CONDITIONS (Note 7)
Rating
Symbol
Min
Max
Unit
Input Voltage
V_IN
V_OUT + V_DO
5.5
V
Bias Voltage
V_BIAS
2.7
5.5
V
Junction Temperature
T_J
−40
125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
7. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
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