NB3N853501E Datasheet, PDF (3/9 Pages) ON Semiconductor – Differential Clock Fanout Buffer Outputs

NB3N853501E
Figure 3. CLK_EN TIMING DIAGRAM
Table 3. ATTRIBUTES (Note 2)
Characteristics
Internal Input Pullup Resistor
Internal Input Pulldown Resistor
ESD Protection
Human Body Model
Machine Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2)
Flammability Rating
Oxygen Index
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Value
50 kW
50 kW
> 2 kV
> 200 V
Level 1
UL 94 V−0 @ 0.125 in
28 to 34
317 Devices
Table 4. MAXIMUM RATINGS (Note 3)
Symbol
Parameter
Condition 1 Condition 2
Rating
Unit
V_CC
Supply Voltage
V_in
Input Voltage
C_in
Input Capacitance
I_out
Output Current
Continuous
Surge
4.6
V
−0.5 v V_I v V_CC + 0.5
V
4
pF
50
mA
100
T_A
Operating Temperature Range, Industrial
T_stg
Storage Temperature Range
q_JA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
TSSOP−20
500 lfpm
−40 to v +85
−65 to +150
140
50
°C
°C
°C/W
q_JA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
Single−Layer
128
PCB (700 mm²,
2 oz)
°C/W
200 lfpm
Multi−Layer
94
PCB (700 mm²,
2 oz)
q_JC
Thermal Resistance (Junction−to−Case)
(Note 4)
TSSOP−20
23 to 41
°C/W
T_sol
Wave Solder
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously.
If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
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