NB2309A_15 Datasheet, PDF (3/9 Pages) ON Semiconductor – 3.3 V Zero Delay Clock Buffer

REF 1
CLKA1 2
CLKA2 3
V_DD ⁴
GND 5
CLKB1 6
CLKB2 7
S2 ₈
NB2309A
NB2309A
16 CLKOUT
15 CLKA4
14 CLKA3
13 V_DD
12 GND
11 CLKB4
10 CLKB3
9 S1
Figure 2. Pin Configuration
Table 2. PIN DESCRIPTION
Pin #
Pin Name
1
REF (Note 2)
2
CLKA1 (Note 3)
3
CLKA2 (Note 3)
4
V_DD
5
GND
6
CLKB1 (Note 3)
7
CLKB2 (Note 3)
8
S2 (Note 4)
9
S1 (Note 4)
10
CLKB3 (Note 3)
11
CLKB4 (Note 3)
12
GND
13
V_DD
14
CLKA3 (Note 3)
15
CLKA4 (Note 3)
16
CLKOUT (Note 3)
2. Weak pulldown.
3. Weak pulldown on all outputs.
4. Weak pullup on these inputs.
Description
Input reference frequency, 5 V tolerant input.
Buffered clock output, Bank A.
Buffered clock output, Bank A.
3.3 V supply.
Ground.
Buffered clock output, Bank B.
Buffered clock output, Bank B.
Select input, bit 2.
Select input, bit 1.
Buffered clock output, Bank B.
Buffered clock output, Bank B.
Ground.
3.3 V supply.
Buffered clock output, Bank A.
Buffered clock output, Bank A.
Buffered output, internal feedback on this pin.
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