MC74VHCT32A Datasheet, PDF (3/8 Pages) ON Semiconductor – QUAD 2 INPUT OR GATE CMOS LOGIC LEVEL SHIFTER

MC74VHCT32A
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
VCC
(V)
TA = 25°C
Min Typ Max
TA ≤ 85°C
Min Max
TA ≤ 125°C
Min Max Unit
VIH
Minimum High–Level
Input Voltage
3.0 1.2
4.5 2.0
5.5 2.0
1.2
1.2
V
2.0
2.0
2.0
2.0
VIL
Maximum Low–Level
Input Voltage
3.0
0.53
0.53
0.53 V
4.5
0.8
0.8
0.8
5.5
0.8
0.8
0.8
VOH
VOL
IIN
Minimum High–Level
Output Voltage
VIN = VIH or VIL
Maximum Low–Level
Output Voltage
VIN = VIH or VIL
Maximum Input
Leakage Current
VIN = VIH or VIL
IOH = –50µA
VIN = VIH or VIL
IOH = –4mA
IOH = –8mA
VIN = VIH or VIL
IOL = 50µA
VIN = VIH or VIL
IOL = 4mA
IOL = 8mA
VIN = 5.5V or GND
3.0 2.9 3.0
2.9
2.9
V
4.5 4.4 4.5
4.4
4.4
3.0 2.58
4.5 3.94
V
2.48
2.34
3.80
3.66
3.0
0.0 0.1
0.1
0.1
V
4.5
0.0 0.1
0.1
0.1
V
3.0
0.36
0.44
0.52
4.5
0.36
0.44
0.52
0 to
±0.1
±1.0
±1.0 µA
5.5
ICC
Maximum Quiescent
VIN = VCC or GND
5.5
Supply Current
2.0
20
40 µA
ICCT
Quiescent Supply
Current
Input: VIN = 3.4V
5.5
1.35
1.50
1.65 mA
IOPD
Output Leakage
VOUT = 5.5V
0.0
0.5
5.0
10 µA
Current
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^tPHL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Cin
Parameter
Test Conditions
Maximum Propagation
Delay, A or B to Y
VCC = 3.3 ± 0.3V
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
Maximum Input Capacitance
TA = 25°C
Min
Typ
Max
5.5
7.9
8.0
11.4
3.8
5.5
5.3
7.5
4
10
TA = – 40 to 85°C
Min
Max Unit
1.0
9.5
ns
1.0
13.0
1.0
6.5
1.0
8.5
10
pF
Typical @ 25°C, VCC = 5.0V
CPD Power Dissipation Capacitance (Note 1.)
22
pF
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR₎ = CPD  VCC  fin + ICC / 4 (per gate). CPD is used to determine the
no–load dynamic power consumption; PD = CPD  VCC2  fin + ICC  VCC.
TEST
POINT
A
tPLH
Y
1.5V
1.5V
3V
GND
tPHL
VOH
VOL
OUTPUT
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
Figure 1. Switching Waveforms
Figure 2. Test Circuit
http://onsemi.com
3