MC74LVX00_14 Datasheet, PDF (3/5 Pages) ON Semiconductor – Quad 2-Input NAND Gate

MC74LVX00
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ AC ELECTRICAL CHARACTERISTICS (Input t_r = t_f = 3.0 ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ T_A = 25°C
T_A = −40 to 85°C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Symbol
Parameter
Test Conditions
Min
Typ
Max
Min
Max
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH,
t_PHL
Propagation Delay, Input to V_CC = 2.7 V
Output
C_L = 15 pF
C_L = 50 pF
5.4
10.1
1.0
12.5
ns
7.9
13.6
1.0
16.0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{VCC=3.3±0.3V CL=15pF}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{CL = 50 pF}
4.1
6.2
1.0
7.5
6.6
9.7
1.0
11.0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tOSHL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^tOSLH
Output−to−Output Skew
(Note 1)
V_CC = 2.7 V
C_L = 50 pF
V_CC = 3.3 ±0.3 V C_L = 50 pF
1.5
1.5
ns
1.5
1.5
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t_OSHL) or LOW−to−HIGH (t_OSLH); parameter
guaranteed by design.
CAPACITIVE CHARACTERISTICS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
Parameter
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Cin InputCapacitance}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{CPD PowerDissipationCapacitance(Note2)}
T_A = 25°C
Min
Typ
Max
T_A = −40 to 85°C
Min
Max
Unit
4
10
10
pF
19
pF
2. C_PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I_CC(OPR) = C_PD  V_CC  f_in + I_CC / 4 (per gate). C_PD is used to determine the
no−load dynamic power consumption; P_D = C_PD  V_CC2  f_in + I_CC  V_CC.
NOISE CHARACTERISTICS (Input t_r = t_f = 3.0 ns, C_L = 50 pF, V_CC = 3.3 V, Measured in SOIC Package)
T_A = 25°C
Symbol
Characteristic
Typ
Max
Unit
V_OLP Quiet Output Maximum Dynamic V_OL
0.3
0.5
V
V_OLV Quiet Output Minimum Dynamic V_OL
−0.3 −0.5
V
V_IHD Minimum High Level Dynamic Input Voltage
2.0
V
V_ILD Maximum Low Level Dynamic Input Voltage
0.8
V
A or B
50%
O
t_PLH
50% V_CC
V_CC
GND
t_PHL
Figure 2. Switching Waveforms
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
C_L*
*Includes all probe and jig capacitance
Figure 3. Test Circuit
ORDERING INFORMATION
Device
Package
Shipping^†
MC74LVX00DR2G
SOIC−14 NB
(Pb−Free)
2500 Tape & Reel
MC74LVX00DTR2G
TSSOP−14*
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
http://onsemi.com
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