MC74HCT574A_14 Datasheet, PDF (3/7 Pages) ON Semiconductor – Octal 3-State Noninverting D Flip-Flop with LSTTL-Compatible Inputs

MC74HCT574A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol
V_IH
V_IL
V_OH
V_OL
I_in
I_CC
I_OZ
Parameter
Minimum High−Level Input Voltage
Maximum Low−Level Input Voltage
Minimum High−Level Output Voltage
Maximum Low−Level Output Voltage
Maximum Input Leakage Current
Maximum Quiescent Supply Current
(per Package)
Maximum Three−State Leakage
Current
Test Conditions
V_out = 0.1 V or V_CC – 0.1 V
|I_out| ≤ 20 mA
V_out = 0.1 V or V_CC – 0.1 V
|I_out| ≤ 20 mA
V_in = V_IH or V_IL
|I_out| ≤ 20 mA
V_in = V_IH or V_IL
|I_out| ≤ 6.0 mA
V_in = V_IH or V_IL
|I_out| ≤ 20 mA
V_in = V_IH or V_IL
|I_out| ≤ 6.0 mA
V_in = V_CC or GND
V_in = V_CC or GND
I_out = 0 mA
V_in = V_IL or V_IH (Note 1)
V_out = V_CC or GND
Guaranteed Limit
V_CC –55 to
V
25_C
≤ 85_C ≤ 125_C Unit
4.5
2.0
2.0
2.0
V
5.5
2.0
2.0
2.0
4.5
0.8
0.8
0.8
V
5.5
0.8
0.8
0.8
4.5
4.4
4.4
4.4
5.5
5.4
5.4
5.4
V
4.5
3.98
3.84
3.7
4.5
0.1
0.1
0.1
5.5
0.1
0.1
0.1
4.5
0.26
0.33
0.4
5.5
±0.1
±1.0
±1.0
mA
mA
5.5
4.0
40
160
5.5
−0.5
–5.0
mA
–10
DI_CC Additional Quiescent Supply Current V_in = 2.4 V, Any One Input
≥ –55_C
25_C to 125_C
V_in = V_CC or GND, Other Inputs
l_out = 0 mA
5.5
2.9
2.4
mA
1. Output in high−impedance state.
AC ELECTRICAL CHARACTERISTICS (V_CC = 5.0 V ±10%, C_L = 50 pF, Input t_r = t_f = 6.0 ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Guaranteed Limit}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
Parameter
– 55 to
25_C
v 85_C v 125_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _fMAX
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tPLH,
t_PHL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tPLZ,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tPHZ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tPZH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^tPZL
t_TLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tTHL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ C_in
Maximum Clock Frequency (50% Duty Cycle) (Figures 2 and 5)
Maximum Propagation Delay, Clock to Q
(Figures 2 and 5)
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
Maximum Propagation Delay Time, Output Enable to Q
(Figures 3 and 6)
Maximum Output Transition Time, Any Output
(Figures 2, 3 and 5)
Maximum Input Capacitance
30
24
20
30
38
45
28
35
42
28
35
42
12
15
18
10
10
10
Unit
MHz
ns
ns
ns
ns
pF
Typical @ 25°C, V_CC = 5.0 V
C_PD Power Dissipation Capacitance (Per Flip−Flop)*
58
pF
* Used to determine the no−load dynamic power consumption: P_D = C_PD V_CC2f + I_CC V_CC.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{TIMING REQUIREMENTS (VCC = 5.0 V ±10%, CL = 50 pF, Input tr = tf = 6.0 ns)}
Guaranteed Limit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{– 55 to 25_C}
v 85_C
v 125_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tsu
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ t_h
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^tw
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{tr, If}
Parameter
Minimum Setup Time, Data to Clock
Minimum Hold Time, Clock to Data
Minimum Pulse Width, Clock
Maximum Input Rise and Fall Times
Figure
4
4
2
2
Min
Max
Min
Max
Min
Max Unit
10
13
15
ns
5.0
5.0
5.0
ns
15
19
22
ns
500
500
500
ns
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