MC74HC4060A_16 Datasheet, PDF (3/11 Pages) ON Semiconductor – 14-Stage Binary Ripple Counter With Oscillator

MC74HC4060A
DC CHARACTERISTICS (Voltages Referenced to GND) (continued)
Symbol
Parameter
Condition
V_CC
Guaranteed Limit
V −55 to 25°C ≤85°C ≤125°C Unit
V_OH Minimum High−Level Output Voltage V_in = V_CC or GND
(Osc Out 1, Osc Out 2)
|I_out| ≤ 20mA
2.0
1.9
4.5
4.4
6.0
5.9
1.9
1.9
V
4.4
4.4
5.9
5.9
V_in =V_CC or GND |I_out| ≤ 0.7mA 3.0
|I_out| ≤ 1.0mA 4.5
|I_out| ≤ 1.3mA 6.0
V_OL Maximum Low−Level Output Voltage V_in = V_CC or GND
2.0
(Osc Out 1, Osc Out 2)
|I_out| ≤ 20mA
4.5
6.0
2.48
3.98
5.48
0.1
0.1
0.1
2.34 2.20
3.84 3.70
5.34 5.20
0.1
0.1
V
0.1
0.1
0.1
0.1
I_in
Maximum Input Leakage Current
I_CC Maximum Quiescent Supply
Current (per Package)
V_in =V_CC or GND |I_out| ≤ 0.7mA 3.0
|I_out| ≤ 1.0mA 4.5
|I_out| ≤ 1.3mA 6.0
V_in = V_CC or GND
6.0
V_in = V_CC or GND
6.0
I_out = 0mA
0.26
0.26
0.26
±0.1
4
0.33 0.40
0.33 0.40
0.33 0.40
±1.0
±1.0
mA
40
160
mA
AC CHARACTERISTICS (C_L = 50 pF, Input t_r = t_f = 6 ns)
Symbol
Parameter
f_max Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
t_PLH,
t_PHL
Maximum Propagation Delay, Osc In to Q4*
(Figures 1 and 4)
t_PLH,
t_PHL
Maximum Propagation Delay, Osc In to Q14*
(Figures 1 and 4)
t_PHL Maximum Propagation Delay, Reset to Any Q
(Figures 2 and 4)
t_PLH,
t_PHL
Maximum Propagation Delay, Qn to Qn+1
(Figures 3 and 4)
V_CC
Guaranteed Limit
V −55 to 25°C ≤85°C ≤125°C Unit
2.0
6.0
3.0
10
4.5
30
6.0
50
9.0
8.0 MHz
14
12
28
25
45
40
2.0
300
3.0
180
4.5
60
6.0
51
375
450
ns
200
250
75
90
64
75
2.0
500
3.0
350
4.5
250
6.0
200
750 1000 ns
450
600
275
300
220
250
2.0
195
3.0
75
4.5
39
6.0
33
245
300
ns
100
125
49
61
42
53
2.0
75
3.0
60
4.5
15
6.0
13
95
125
ns
75
95
19
24
16
20
AC CHARACTERISTICS (C_L = 50 pF, Input t_r = t_f = 6 ns) − continued
Symbol
Parameter
V_CC
Guaranteed Limit
V −55 to 25°C ≤85°C ≤125°C Unit
t_TLH,
t_THL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
75
3.0
27
4.5
15
6.0
13
95
110
ns
32
36
19
22
16
19
C_in Maximum Input Capacitance
10
10
10
pF
* For T_A = 25°C and C_L = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:
V_CC = 2.0 V: t_P = [93.7 + 59.3 (n−1)] ns
V_CC = 4.5 V: t_P = [30.25 + 14.6 (n−1)] ns
V_CC = 3.0 V: t_P = [61.5+ 34.4 (n−1)] ns
V_CC = 6.0 V: t_P = [24.4 + 12 (n−1)] ns
Typical @ 25°C, V_CC = 5.0 V
C_PD Power Dissipation Capacitance (Per Package)*
35
pF
* Used to determine the no−load dynamic power consumption: P_D = C_PD V_CC2f + I_CC V_CC.
www.onsemi.com
3