MC74HC4046A Datasheet, PDF (3/16 Pages) ON Semiconductor – Phase-Locked Loop

MC74HC4046A
[Phase Comparator Section]
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
VIH
VIL
VOH
Minimum High–Level Input
Voltage DC Coupled
SIGIN, COMPIN
Maximum Low–Level Input
Voltage DC Coupled
SIGIN, COMPIN
Minimum High–Level
Output Voltage
PCPOUT, PCnOUT
Test Conditions
Vout = 0.1 V or VCC – 0.1 V
|Iout| ≤ 20 µA
Vout = 0.1 V or VCC – 0.1 V
|Iout| ≤ 20 µA
Vin = VIH or VIL
|Iout| ≤ 20 µA
Vin = VIH or VIL
|Iout| ≤ 4.0 mA
|Iout| ≤ 5.2 mA
VCC
Volts
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
Guaranteed Limit
– 55 to
25_C
≤ 85°C ≤ 125°C Unit
1.5
1.5
1.5
V
3.15
3.15
3.15
4.2
4.2
4.2
0.5
0.5
0.5
V
1.35
1.35
1.35
1.8
1.8
1.8
1.9
1.9
1.9
V
4.4
4.4
4.4
5.9
5.9
5.9
3.98
3.84
3.7
5.48
5.34
5.2
(continued)
[Phase Comparator Section]
DC ELECTRICAL CHARACTERISTICS – continued (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
Volts
– 55 to
25_C
≤ 85°C ≤ 125°C Unit
VOL
Maximum Low–Level
Output Voltage Qa–Qh
PCPOUT, PCnOUT
Vout = 0.1 V or VCC – 0.1 V
|Iout| ≤ 20 µA
2.0
0.1
4.5
0.1
6.0
0.1
0.1
0.1
V
0.1
0.1
0.1
0.1
Vin = VIH or VIL
|Iout| ≤ 4.0 mA
|Iout| ≤ 5.2 mA
Iin
Maximum Input Leakage Cur- Vin = VCC or GND
rent
SIGIN, COMPIN
4.5
0.26
6.0
0.26
0.33
0.4
0.33
0.4
2.0
± 3.0
± 4.0
± 5.0
µA
3.0
± 7.0
± 9.0
± 11.0
4.5
± 18.0
± 23.0
± 27.0
6.0
± 30.0
± 38.0
± 45.0
IOZ
Maximum Three–State
Leakage Current
PC2OUT
Output in High–Impedance State 6.0
Vin = VIH or VIL
Vout = VCC or GND
ICC
Maximum Quiescent Supply
Vin = VCC or GND
6.0
Current (per Package)
|Iout| = 0 µA
(VCO disabled)
Pins 3, 5 and 14 at VCC
Pin 9 at GND; Input Leakage
at
Pins 3 and 14 to be excluded
± 0.5
4.0
± 5.0
± 10
µA
40
160
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
[Phase Comparator Section]
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol
Parameter
VCC
Volts
Guaranteed Limit
– 55 to 25_C
≤ 85°C
≤ 125°C Unit
tPLH, Maximum Propagation Delay, SIGIN/COMPIN to PC1OUT
2.0
175
tPHL
(Figure 1)
4.5
35
6.0
30
220
265
ns
44
53
37
45
tPLH, Maximum Propagation Delay, SIGIN/COMPIN to PCPOUT
2.0
340
tPHL
(Figure 1)
4.5
68
6.0
58
425
510
ns
85
102
72
87
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