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MC74HC00A_13 Datasheet, PDF (3/7 Pages) ON Semiconductor – Quad 2-Input NAND Gate
MC74HC00A
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Condition
Guaranteed Limit
VCC
V −55 to 25°C ≤85°C ≤125°C Unit
VIH
Minimum High−Level Input
Voltage
Vout = 0.1V or VCC −0.1V
|Iout| ≤ 20mA
2.0
1.50
1.50 1.50
V
3.0
2.10
2.10 2.10
4.5
3.15
3.15 3.15
6.0
4.20
4.20 4.20
VIL
Maximum Low−Level Input
Voltage
Vout = 0.1V or VCC − 0.1V
|Iout| ≤ 20mA
2.0
0.50
0.50 0.50
V
3.0
0.90
0.90 0.90
4.5
1.35
1.35 1.35
6.0
1.80
1.80 1.80
VOH
Minimum High−Level Output
Voltage
Vin = VIH or VIL
|Iout| ≤ 20mA
2.0
1.9
4.5
4.4
6.0
5.9
1.9
1.9
V
4.4
4.4
5.9
5.9
VOL
Maximum Low−Level Output
Voltage
Vin =VIH or VIL
Vin = VIH or VIL
|Iout| ≤ 20mA
|Iout| ≤ 2.4mA 3.0
|Iout| ≤ 4.0mA 4.5
|Iout| ≤ 5.2mA 6.0
2.0
4.5
6.0
2.48
3.98
5.48
0.1
0.1
0.1
2.34 2.20
3.84 3.70
5.34 5.20
0.1
0.1
V
0.1
0.1
0.1
0.1
Iin
Maximum Input Leakage
Current
Vin = VIH or VIL
|Iout| ≤ 2.4mA 3.0
|Iout| ≤ 4.0mA 4.5
|Iout| ≤ 5.2mA 6.0
Vin = VCC or GND
6.0
0.26
0.26
0.26
±0.1
0.33 0.40
0.33 0.40
0.33 0.40
±1.0
±1.0
mA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0mA
6.0
1.0
10
40
mA
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
tPLH,
tPHL
Parameter
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
Cin
Maximum Input Capacitance
Guaranteed Limit
VCC
V −55 to 25°C ≤85°C
≤125°C Unit
2.0
75
3.0
30
4.5
15
6.0
13
95
110
ns
40
55
19
22
16
19
2.0
75
3.0
27
4.5
15
6.0
13
95
110
ns
32
36
19
22
16
19
10
10
10
pF
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
CPD
Power Dissipation Capacitance (Per Buffer)*
22
pF
* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.
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