KLI-2113-D Datasheet, PDF (3/18 Pages) ON Semiconductor – Linear CCD Image Sensor

KLI−2113
DEVICE DESCRIPTION
LS
LOGn
Photodiode Array
TG1
IG
TG2
2 Blank
ID
CCD Cells
f2
f1
12 Test
2098 Active Pixels
12 Dark
fR
RD
VDD
4 Blank
FD
CCD Cells
Figure 2. Single Channel Schematic
f2s SUB
SUB
VIDn
Exposure Control
Exposure control is implemented by selectively clocking
the LOG gates during portions of the scanning line time. By
applying a large enough positive bias to the LOG gate,
the channel potential is increased to a level beyond the
‘pinning level’ of the photodiode. (The ‘pinning’ level is the
maximum channel potential that the photodiode can achieve
and is fixed by the doping levels of the structure.) With TG1
in an ‘off’ state and LOG strongly biased, all of the
photocurrent will be drawn off to the LS drain. Referring to
Figure 9, one notes that the exposure can be controlled by
pulsing the LOG gate to a ‘high’ level while TG1 is turning
‘off’ and then returning the LOG gate to a ‘low’ bias level
sometime during the line scan. The effective exposure (t_EXP)
is the net time between the falling edge of the LOG gate and
the falling edge of the TG1 gate (end of the line). Separate
LOG connections for each channel are provided, enabling
on-chip light source and image spectral color balancing. As
a cautionary note, the switching transients of the LOG gates
during line readout may inject an artifact at the sensor
output. Rising edge artifacts can be avoided by switching
LOG during the photodiode-to-CCD transfer period,
preferably, during the TG1 falling edge. Depending on
clocking speeds, the falling edge of the LOG should be
synchronous with the f1/f2 shift register readout clocks.
For very fast applications, the falling edge of the LOG gate
may be limited by on-chip RC delays across the array. In this
case, artifacts may extend across one or more pixels.
Correlated double sampling (CDS) processing of the output
waveform can remove the first order magnitude of such
artifacts. In high dynamic range applications, it may be
advisable to limit the LOG fall times to minimize the current
transients in the device substrate and limit the magnitude of
the artifact to an acceptable level.
Pixel Summing
The effective resolution of this sensor can be varied by
enabling the pixel summing feature. A separate pin is
provided for the last shift register gate labeled f2s. This
gate, when clocked appropriately, stores the summation of
signal from adjacent pixels. This combined charge packet is
then transferred onto the sense node. As an example,
the sensor can be operated in 2-pixel summing mode
(1,049 pixels), by supplying a f2s clock which is a 75% duty
cycle signal at 1/2 the frequency of the f2 signal, and
modifying the fR clock as depicted in Figure 10.
Applications that require full resolution mode
(2,098 pixels), must tie the f2s pin to the f2 pin. Refer to
Figure 9 and Figure 10 for additional details.
Image Acquisition
During the integration period, an image is obtained by
gathering electrons generated by photons incident upon the
photodiodes. The charge collected in the photodiode array
is a linear function of the local exposure. The charge is stored
in the photodiode itself and is isolated from the CCD shift
registers during the integration period by the transfer gates
TG1 and TG2, which are held at barrier potentials. At the
end of the integration period, the CCD register clocking is
stopped with the f1 and f2 gates being held in a ‘high’ and
‘low’ state respectively. Next, the TG gates are turned ‘on’
causing the charge to drain from the photo-diode into the
TG1 storage region. As TG1 is turned back ‘off’, charge is
transferred through TG2 and into the f1 storage region.
The TG2 gate is then turned ‘off’, isolating the shift registers
from the accumulation region once again. Complementary
clocking of the f1 and f2 phases now resumes for readout
of the current line of data while the next line of data is
integrated.
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