CM3202-00 Datasheet, PDF (3/11 Pages) ON Semiconductor – VTT Termination Voltage Regulator

CM3202−00
PACKAGE / PINOUT DIAGRAMS
Top View
(Pins Down View)
Pin 1
Marking
VIN 1
8
Thermal Pad
VDDQ
NC 2
VTT 3
7 ADJSD
6 GND
NC 4
5 GND
Bottom View
(Pins Up View)
8
1
7 _GND 2
6 ^PAD 3
5
4
8−Lead WDFN Package
CM3202−00DE
Table 1. PIN DESCRIPTIONS
Lead(s)
Name
Description
1
VIN
Input supply voltage pin. Bypass with a 220 mF capacitor to GND.
2
NC
Not internally connected. For better heat flow, connect to GND (exposed pad).
3
VTT
V_TT regulator output pin, which is preset to 50% of V_DDQ.
4
NC
Not internally connected. For better heat flow, connect to GND (exposed pad).
5
GND Ground pin (analog).
6
GND Ground pin (power).
This pin is for V_DDQ output voltage adjustment. It is available as long as V_DDQ is enabled.
During Manual/Thermal shutdown, it is tightened to GND. The V_DDQ output voltage is set
using an external resistor divider connected to ADJSD:
7
ADJSD ^{VDDQ = 1.25 V × ((R1 + R2) / R2)}
Where R1 is the upper resistor and R2 is the ground−side resistor. In addition, the ADJSD pin functions as
a Shutdown pin. When ADJSD voltage is higher than 2.7 V (SHDN_H), the circuit is in Shutdown mode.
When ADJSD voltage is below 1.5 V (SHDN_L), both VDDQ and VTT are enabled. A low−leakage Schottky
diode in series with ADJSD pin is recommended to avoid interference with the voltage adjustment setting.
8
EPad
VDDQ
GND
V_DDQ regulator output voltage pin.
The backside exposed pad which serves as the package heatsink. Must be connected to GND.
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