CAV24C02YE-GT3 Datasheet, PDF (3/11 Pages) ON Semiconductor – 2-Kb, 4-Kb, 8-Kb and 16-Kb I2C CMOS Serial EEPROM

CAV24C02, CAV24C04, CAV24C08, CAV24C16
Table 4. PIN IMPEDANCE CHARACTERISTICS (V_CC = 2.5 V to 5.5 V, T_A = −40°C to +125°C, unless otherwise specified.)
Symbol
Parameter
Conditions
Max
Units
C_IN (Note 4)
SDA Pin Capacitance
Other Pins
V_IN = 0 V, f = 1.0 MHz, V_CC = 5.0 V
8
pF
6
pF
I_WP (Note 5)
WP Input Current
V_IN < V_IH, V_CC = 5.5 V
130
mA
V_IN < V_IH, V_CC = 3.6 V
120
V_IN < V_IH, V_CC = 2.5 V
80
V_IN > V_IH
2
I_A (Note 5)
Address Input Current
(A0, A1, A2)
Product Rev H
V_IN < V_IH, V_CC = 5.5 V
V_IN < V_IH, V_CC = 3.6 V
V_IN < V_IH, V_CC = 2.5 V
50
mA
35
25
V_IN > V_IH
2
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V_CC), the strong pull−down reverts to a weak current source.
Table 5. A.C. CHARACTERISTICS (Note 6) (V_CC = 2.5 V to 5.5 V, T_A = −40°C to +125°C, unless otherwise specified.)
Standard
Fast
Symbol
Parameter
Min
Max
Min
Max
Units
F_SCL
Clock Frequency
100
400
kHz
t_HD:STA
START Condition Hold Time
4
0.6
ms
t_LOW
Low Period of SCL Clock
4.7
1.3
ms
t_HIGH
High Period of SCL Clock
4
0.6
ms
t_SU:STA
START Condition Setup Time
4.7
0.6
ms
t_HD:DAT
Data In Hold Time
0
0
ms
t_SU:DAT
Data In Setup Time
250
100
ns
t_R
SDA and SCL Rise Time
1000
300
ns
t_F (Note 6)
SDA and SCL Fall Time
300
300
ns
t_SU:STO
STOP Condition Setup Time
4
0.6
ms
t_BUF
Bus Free Time Between STOP and START
4.7
1.3
ms
t_AA
SCL Low to Data Out Valid
3.5
0.9
ms
t_DH
Data Out Hold Time
100
100
ns
T_i (Note 6)
Noise Pulse Filtered at SCL and SDA Inputs
100
100
ns
t_SU:WP
WP Setup Time
0
0
ms
t_HD:WP
WP Hold Time
2.5
2.5
ms
t_WR
Write Cycle Time
5
5
ms
t_PU (Notes 7, 8) Power−up to Ready Mode
1
1
ms
6. Test conditions according to “AC Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. t_PU is the delay between the time V_CC is stable and the device is ready to accept commands.
Table 6. A.C. TEST CONDITIONS
Input Drive Levels
Input Rise and Fall Time
0.2 x V_CC to 0.8 x V_CC
v 50 ns
Input Reference Levels
Output Reference Level
Output Test Load
0.3 x V_CC, 0.7 x V_CC
0.5 x V_CC
Current Source I_OL = 3 mA; C_L = 100 pF
http://onsemi.com
3