CAT93C86W Datasheet, PDF (3/10 Pages) ON Semiconductor – 16 Kb Microwire Serial EEPROM

CAT93C86
Table 4. PIN CAPACITANCE (Note 5)
Symbol
Test
C_OUT
C_IN
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
Conditions
V_OUT = 0 V
V_IN = 0 V
Min
Typ
Max
Units
5
pF
5
pF
Table 5. POWER−UP TIMING (Notes 5, 6)
Symbol
Parameter
t_PUR
t_PUW
Power−up to Read Operation
Power−up to Write Operation
Max
Units
1
ms
1
ms
Table 6. A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
≤ 50 ns
0.4 V to 2.4 V
0.8 V, 2.0 V
0.2 x V_CC to 0.7 x V_CC
0.5 x V_CC
4.5 V ≤ V_CC ≤ 5.5 V
4.5 V ≤ V_CC ≤ 5.5 V
1.8 V ≤ V_CC ≤ 4.5 V
1.8 V ≤ V_CC ≤ 4.5 V
Table 7. A.C. CHARACTERISTICS
V_CC =
1.8 V − 5.5 V
V_CC =
2.5 V − 5.5 V
V_CC =
4.5 V − 5.5 V
Symbol
Parameter
Test Conditions
Min Max Min Max Min Max
t_CSS
CS Setup Time
200
100
50
t_CSH
CS Hold Time
0
0
0
t_DIS
DI Setup Time
200
100
50
t_DIH
DI Hold Time
200
100
50
t_PD1
Output Delay to 1
1
0.5
t_PD0
Output Delay to 0
C_L = 100 pF (Note 7)
1
0.5
t_HZ (Note 5) Output Delay to High−Z
400
200
t_EW
Program/Erase Pulse Width
5
5
t_CSMIN
Minimum CS Low Time
1
0.5
0.15
t_SKHI
Minimum SK High Time
1
0.5
0.15
t_SKLOW
Minimum SK Low Time
1
0.5
0.15
t_SV
Output Delay to Status Valid
1
0.5
SK_MAX
Maximum Clock Frequency
DC 500 DC 1000 DC
5. These parameters are tested initially and after a design or process change that affects the parameter.
6. t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified operation can be initiated.
7. The input levels and timing reference points are shown in the “A.C. Test Conditions” table.
0.15
0.15
100
5
0.1
3000
Units
ns
ns
ns
ns
ms
ms
ns
ms
ms
ms
ms
ms
kHz
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