CAT93C86 Datasheet, PDF (3/13 Pages) Catalyst Semiconductor – 16K-Bit Microwire Serial EEPROM

CAT93C86 (Rev. C)
PIN CAPACITANCE ⁽¹⁾
Symbol
C_OUT
C_IN
Test
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
POWER-UP TIMING ⁽¹⁾⁽²⁾
Symbol
t_PUR
t_PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Conditions
V_OUT = 0V
V_IN = 0V
Min Typ
Max
5
5
Units
pF
pF
Max
Units
1
ms
1
ms
A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
≤ 50ns
0.4V to 2.4V
0.8V, 2.0V
0.2V_CC to 0.7V_CC
0.5V_CC
4.5V ≤ V_CC ≤ 5.5V
4.5V ≤ V_CC ≤ 5.5V
1.8V ≤ V_CC ≤ 4.5V
1.8V ≤ V_CC ≤ 4.5V
A.C. CHARACTERISTICS
Symbol Parameter
Test
Conditions
t_CSS
t_CSH
t_DIS
t_DIH
t_PD1
t_PD0
t_HZ(1)
t_EW
t_CSMIN
t_SKHI
t_SKLOW
t_SV
SK_MAX
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
C_L = 100pF⁽³⁾
V_CC =
1.8V-5.5V
Min Max
200
0
200
200
1
1
400
5
1
1
1
1
DC 500
V_CC =
2.5V-5.5V
Min Max
100
0
100
100
0.5
0.5
200
5
0.5
0.5
0.5
0.5
DC 1000
V_CC =
4.5V-5.5V
Min Max
50
0
50
50
0.15
0.15
100
5
0.15
0.15
0.15
0.1
DC 3000
Units
ns
ns
ns
ns
µs
µs
ns
ms
µs
µs
µs
µs
kHz
Notes:
(1) These parameters are tested initially and after a design or process change that affects the parameter.
(2) t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified operation can be initiated.
(3) The input levels and timing reference points are shown in the “AC Test Conditions” table.
© 2008 SCILLC. All rights reserved
3
Characteristics subject to change without notice
Doc. No. MD-1091 Rev. R