CAT93C66VE Datasheet, PDF (3/16 Pages) ON Semiconductor – 4 kb Microwire Serial CMOS EEPROM

CAT93C66, CAT93W66
Table 5. D.C. OPERATING CHARACTERISTICS − NEW PRODUCT (REV H)
(V_CC = +1.8 V to +5.5 V, T_A=−40°C to +125°C unless otherwise specified.)
Symbol
Parameter
Test Conditions
I_CC1
I_CC2
I_SB1
I_SB2
I_LI
I_LO
V_IL1
V_IH1
V_IL2
V_IH2
V_OL1
V_OH1
V_OL2
V_OH2
Supply Current (Write)
Supply Current (Read)
Standby Current
(x8 Mode)
Standby Current
(x16 Mode)
Input Leakage Current
Output Leakage
Current
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Write, V_CC = 5.0 V
Read, DO open, f_SK = 2 MHz, V_CC = 5.0 V
V_IN = GND or V_CC
CS = GND, ORG = GND
T_A = −40°C to +85°C
T_A = −40°C to +125°C
V_IN = GND or V_CC
CS = GND,
ORG = Float or V_CC
T_A = −40°C to +85°C
T_A = −40°C to +125°C
V_IN = GND to V_CC
T_A = −40°C to +85°C
T_A = −40°C to +125°C
V_OUT = GND to V_CC
CS = GND
T_A = −40°C to +85°C
T_A = −40°C to +125°C
4.5 V ≤ V_CC < 5.5 V
4.5 V ≤ V_CC < 5.5 V
1.8 V ≤ V_CC < 4.5 V
1.8 V ≤ V_CC < 4.5 V
4.5 V ≤ V_CC < 5.5 V, I_OL = 3 mA
4.5 V ≤ V_CC < 5.5 V, I_OH = −400 mA
1.8 V ≤ V_CC < 4.5 V, I_OL = 1 mA
1.8 V ≤ V_CC < 4.5 V, I_OH = −100 mA
Min
−0.1
2
0
V_CC x 0.7
2.4
V_CC − 0.2
Max
1
500
2
5
1
3
1
2
1
2
0.8
V_CC + 1
V_CC x 0.2
V_CC + 1
0.4
0.2
Units
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
V
V
Table 6. PIN CAPACITANCE (T_A = 25°C, f = 1.0 MHz, V_CC = +5.0 V)
Symbol
Test
Conditions
Min
Typ
Max
Units
C_OUT (Note 5)
Output Capacitance (DO)
V_OUT = 0 V
5
pF
C_IN (Note 5)
Input Capacitance (CS, SK, DI, ORG)
V_IN = 0 V
5
pF
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
Table 7. POWER−UP TIMING (Notes 6, 7)
Symbol
Parameter
Max
Units
t_PUR
Power−up to Read Operation
1
ms
t_PUW
Power−up to Write Operation
1
ms
6. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC−Q100 and JEDEC test methods.
7. t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified operation can be initiated.
Table 8. A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
Output Load
≤ 50 ns
0.4 V to 2.4 V
0.8 V, 2.0 V
0.2 V_CC to 0.7 V_CC
0.5 V_CC
Current Source I_OLmax/I_OHmax; CL = 100 pF
4.5 V ≤ V_CC ≤ 5.5 V
4.5 V ≤ V_CC ≤ 5.5 V
1.8 V ≤ V_CC ≤ 4.5 V
1.8 V ≤ V_CC ≤ 4.5 V
http://onsemi.com
3