CAT93C46LI-G Datasheet, PDF (3/16 Pages) ON Semiconductor – 1 kb Microwire Serial EEPROM

CAT93C46
Table 4. D.C. OPERATING CHARACTERISTICS − NEW PRODUCT (REV P)
(V_CC = +1.8 V to +5.5 V, T_A = −40°C to +125°C, V_CC = +1.65 V to +5.5 V, T_A = −20°C to +85°C unless otherwise specified.)
Symbol
Parameter
Test Conditions
Min
Max
I_CC1
I_CC2
I_SB1
I_SB2
I_LI
I_LO
V_IL1
V_IH1
V_IL2
V_IH2
V_OL1
V_OH1
V_OL2
V_OH2
Supply Current (Write)
Supply Current (Read)
Standby Current
(x8 Mode)
Standby Current
(x16 Mode)
Input Leakage Current
Output Leakage
Current
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Write, V_CC = 5.0 V
Read, DO open, f_SK = 2 MHz, V_CC = 5.0 V
V_IN = GND or V_CC
CS = GND, ORG = GND
T_A = −40°C to +85°C
T_A = −40°C to +125°C
V_IN = GND or V_CC
CS = GND,
ORG = Float or V_CC
T_A = −40°C to +85°C
T_A = −40°C to +125°C
V_IN = GND to V_CC
T_A = −40°C to +85°C
T_A = −40°C to +125°C
V_OUT = GND to V_CC
CS = GND
T_A = −40°C to +85°C
T_A = −40°C to +125°C
4.5 V ≤ V_CC < 5.5 V
4.5 V ≤ V_CC < 5.5 V
1.8 V ≤ V_CC < 4.5 V
1.8 V ≤ V_CC < 4.5 V
4.5 V ≤ V_CC < 5.5 V, I_OL = 3 mA
4.5 V ≤ V_CC < 5.5 V, I_OH = −400 mA
1.8 V ≤ V_CC < 4.5 V, I_OL = 1 mA
1.8 V ≤ V_CC < 4.5 V, I_OH = −100 mA
−0.1
2
0
V_CC x 0.7
2.4
V_CC − 0.2
1
500
2
5
1
3
1
2
1
2
0.8
V_CC + 1
V_CC x 0.2
V_CC + 1
0.4
0.2
Units
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
V
V
Table 5. PIN CAPACITANCE (T_A = 25°C, f = 1 MHz, V_CC = 5 V)
Symbol
Test
Conditions
Min
Typ
Max Units
C_OUT (Note 4) Output Capacitance (DO)
V_OUT = 0 V
5
pF
C_IN (Note 4)
Input Capacitance (CS, SK, DI, ORG)
V_IN = 0 V
5
pF
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
Table 6. A.C. CHARACTERISTICS − MATURE PRODUCT (Not Recommended for New Designs)
(V_CC = +1.8 V to +5.5 V, T_A = −40°C to +85°C, unless otherwise specified.) (Note 5)
Symbol
Parameter
Min Limit
Max Limit
Units
t_CSS
CS Setup Time
50
ns
t_CSH
CS Hold Time
0
ns
t_DIS
DI Setup Time
100
ns
t_DIH
DI Hold Time
100
ns
t_PD1
Output Delay to 1
0.25
ms
t_PD0
Output Delay to 0
0.25
ms
t_HZ (Note 6)
Output Delay to High−Z
100
ns
t_EW
Program/Erase Pulse Width
5
ms
t_CSMIN
Minimum CS Low Time
0.25
ms
t_SKHI
Minimum SK High Time
0.25
ms
t_SKLOW
Minimum SK Low Time
0.25
ms
t_SV
Output Delay to Status Valid
0.25
ms
SK_MAX
Maximum Clock Frequency
DC
2000
kHz
5. Test conditions according to “AC Test Conditions” table.
6. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
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