CAT884 Datasheet, PDF (3/8 Pages) ON Semiconductor – Quad Voltage Supervisor

CAT884
Table 3. ELECTRICAL CHARACTERISTICS
(V_DD = 1.0 V to 5.5 V, T_A = −40°C to +85°C, unless otherwise noted. Typical values are at V_DD = 3.0 V to 3.3 V, T_A = +25°C. (Note 1))
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
V_DD
I_DD
V_{POR_}
Operating Voltage
Supply Current
V_DD Input Voltage Threshold
RESET OUTPUT
V_DD = 5 V
V_DD low ³ High
V_DD High ³ Low
1.5
5.5
V
3
9
mA
2.6
V
2.4
V_OL
RESET Output Low
RIN
Internal Pull−Up Resistor
V_CC ≥ 5 V, I_SINK = 2.5 mA
V_CC < 3.3 V, I_SINK = 1.5 mA
0.05
0.4
V
0.05
0.4
20
kW
TCV_TH
Reset Threshold Temperature
Coefficient
60
ppm/°C
t_RPD
Delay; V_IN to Reset
V_IN falling at 10 mV/ms from V_TH to
1
1.5
ms
(V_TH – 50 mV)
VOLTAGE THRESHOLD
V_TH
V_HYST
Adjustable Threshold
Reset Threshold Hysteresis
Monitored voltage decreasing
0.619 0.635 0.651
V
Monitored voltage increasing compared
10
mV
to monitored voltage decreasing
V_{TH_VAR} Variance of V_TH voltages
V_TH (max) − V_TH (min) (Note 4)
1.8
mV
t_FIL
Glitch Filter Delay
V_MON glitch to RST low Filter
30
ms
t_RD
Delay; V_MON to Reset
V_MON falling at 10 mV/ms from V_TH to
1
2
ms
(V_TH – 50 mV)
MANUAL RESET INPUT
VTHL
MR Input Voltage Low
0.8
V
VTHH MR Input Voltage High
VDD −
V
0.6
T_PW
MR Minimum Pulse Width
IPU
Pull−Up Current
20
ns
10
mA
t_MD
MR to Deassert Reset output
delay
40
ns
t_MR
MR to Assert Reset output
delay
30
ns
1. 100% production tested at T_A = +25°C. Limits over temperature guaranteed by design.
2. The devices are powered from V_DD.
3. The RESET output is guaranteed to be in the correct state for V_DD down to 1 V.
4. Not tested in production but guaranteed by design.
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