CAT8836 Datasheet, PDF (3/7 Pages) ON Semiconductor – NanoPower Supervisory Circuit

CAT8836
Table 4. ELECTRICAL CHARACTERISTICS (Over recommended operating conditions, unless otherwise noted.)
Parameter
Symbol
Test Conditions
Min
Typ Max Unit
RESET high−level output voltage
RESET Low−level output voltage
RESET power−up voltage
(Note 3)
V_OH
V_OL
V_DD = 3.3 V, I_OH = −2 mA
V_DD = 1.8 V, I_OL = 1 mA
V_DD = 3.3 V, I_OL = 2 mA
V_DD ≥ 1.1 V, I_OL = 50 mA
0.8 × V_DD
V
0.4
V
0.2
V
Negative−going input threshold
CAT8836E18
V_TH
voltage (Note 4)
CAT8836J25
T_A = −40°C to +85°C
1.66
1.71 1.74
V
2.18
2.25 2.29
V
CAT8836H30
2.70
2.79 2.85
V
CAT8836L30
2.56
2.64 2.69
V
CAT8836K33
2.84
2.93 2.99
V
Hysteresis at V_DD input
Input high−level current
MR (Note 5)
V_HYS
I_IH
1.7 V < V_IT < 2.5 V
2.5 V < V_IT < 3.5 V
MR = 0.7 × V_DD,
V_DD = 5.5 V
30
mV
40
−40
−60 −100 mA
CT
CT = V_DD = 5.5 V
−25
+25 nA
Input low−level current
MR (Note 5)
I_IL
MR = 0 V, V_DD = 5.5 V
−130
−200 −340 mA
CT
CT = 0 V, V_DD = 5.5 V
−25
+25 nA
Supply current
I_DD
V_DD > V_TH, V_DD < 3 V
220 400 nA
V_DD > V_TH, V_DD > 3 V
250 450
V_DD < V_TH
10
15
mA
Internal pull−up resistor at MR
R_IN
30
kW
Input capacitance at MR and CT
C_I
V_I = 0 V to V_DD
5
pF
3. The lowest voltage at which the RESET output becomes active. t_R, V_DD ≥ 15 ms/V.
4. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 mF) should be placed near the supply terminal.
5. If manual reset is unused, MR should be connected to V_DD to minimize current consumption.
Table 5. SWITCHING CHARACTERISTICS (At T_A = +25°C, R_L = 1 MW, and C_L = 50 pF, unless otherwise noted.)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Delay time
t_PD
V_DD ≥ V_TH + 0.2 V,
5
10
15
ms
MR = 0.7 × V_DD, CT = GND
V_DD ≥ V_TH + 0.2 V,
100 200 300
MR = 0.7 × V_DD, CT = V_DD
Propagation (delay) time,
V_DD to RESET delay
t_PHL
high−to−low−level output
V_IL = V_TH − 0.2 V,
V_IH = V_TH + 0.2 V
10
ms
Propagation (delay) time,
high−to−low−level output
MR to RESET delay
t_MHL
V_IL = 1.6 V
V_DD ≥ V_TH + 0.2 V,
V_IL = 0.3 × V_DD,
V_IH = 0.7 × V_DD
50
100
ns
Table 6. TIMING REQUIREMENTS (At T_A = +25°C, R_L = 1 MW, and C_L = 50 pF, unless otherwise noted.)
Parameter
Symbol
Test Conditions
Min Typ
Pulse width
at V_DD
at MR
t_W
V_IH = V_TH + 0.2 V, V_IL = V_TH – 0.2 V
6
t_WR
V_DD ≥ V_TH + 0.2 V, V_IL = 0.3 × V_DD, V_IH = 0.7 × V_DD
1
Max Unit
ms
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