CAT824_12 Datasheet, PDF (3/12 Pages) ON Semiconductor – System Supervisory Voltage Reset

CAT823, CAT824, CAT825
Table 3. ELECTRICAL OPERATING CHARACTERISTICS (DC Characteristics: V_CC = 3.0 V to 5.5 V for L/M versions;
V_CC = 2.0 V to 3.6 V for the R/S/T/U/Y/Z version, −40°C ≤ T_A ≤ +85°C unless otherwise noted. Typical Values at T_A = 25°C and V_CC = 5 V
for L/M versions; V_CC = 3.3 V for the T/S versions; V_CC = 3.0 V for the R version; and V_CC = 2.5 V for the U/Y/Z versions.) (Note 1)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
I_CC
Supply Current
CAT823 (L/M Versions)
CAT824 (L/M Versions)
6
17
mA
CAT823 (R/S/T/Y/Z Versions)
CAT824 (R/S/T/U/Y/Z Versions)
4
12
CAT825 (L/M Versions)
3
8
CAT825 (R/S/T/Y/Z Versions)
2
6
V_RST
Reset Threshold
Reset Threshold Tempco
CAT82_L at −40°C ≤ T_A ≤ +85°C
CAT82_M at −40°C ≤ T_A ≤ +85°C
CAT82_T at −40°C ≤ T_A ≤ +85°C
CAT82_S at −40°C ≤ T_A ≤ +85°C
CAT82_R at −40°C ≤ T_A ≤ +85°C
CAT82_Z at −40°C ≤ T_A ≤ +85°C
CAT82_Y at −40°C ≤ T_A ≤ +85°C
CAT824U at −40°C ≤ T_A ≤ +85°C
4.50
4.63
4.75
V
4.25
4.38
4.50
3.00
3.08
3.15
2.85
2.93
3.00
2.55
2.63
2.70
2.25
2.32
2.38
2.13
2.19
2.25
1.95
2.00
2.05
40
ppm/°C
Reset Threshold Hysteresis CAT82_L/M
10
mV
CAT82_R/S/T/Y/Z, CAT824U
5
t_RD
V_CC to Reset Delay (Note 2) V_CC = V_TH to (V_TH − 100 mV)
20
ms
t_RP
Reset Active Timeout Period
140
200
400
ms
V_OH
RESET Output High Voltage CAT82_L/M, V_CC = V_{RST max},
V_CC − 1.5 V
V
I_SOURCE = −120 mA
CAT82_T/S/R/Z/Y, CAT824U,
V_CC = V_{RST max}, I_SOURCE = −30 mA
0.8 x V_CC
V_OL
RESET Output Low Voltage CAT82_L/M, V_CC = V_{RST min},
I_SINK = 3.2 mA
0.4
V
CAT82_T/S/R/Z/Y, CAT824U,
0.3
V_CC = V_{RST min}, I_SINK = 1.2 mA
T_A = 0°C to +70°C, V_CC = 1 V,
0.3
V_CC falling, I_SINK = 50 mA
T_A = T_MIN to T_MAX, V_CC = 1.2 V,
0.3
V_CC falling, I_SINK = 100 mA
I_SOURCE
RESET Output
Short−Circuit Current
CAT82_L/M, Reset = 0 V, V_CC = 5.5 V
CAT82_L/M, Reset = 0 V, V_CC = 3.6 V
1.5
mA
0.8
V_OH
Reset Output Voltage
V_CC > 1.8 V, I_SOURCE = −150 mA
0.8 x V_CC
V
V_OL
CAT824L/M & CAT825L/M,
0.4
V_CC = V_{RST max}, I_SINK = 3.2 mA
CAT824R/S/T/U/Y/Z &
0.3
CAT825R/S/T/Y/Z,
V_CC = V_{RST max}, I_SINK = 1.2 mA
1. Over−temperature limits are guaranteed by design and not production tested.
2. The RESET short−circuit current is the maximum pull−up current when reset is driven low by a bidirectional output.
3. WDI is internally serviced within the watchdog period if WDI is left open.
4. The WDI input current is specified as an average input current when the WDI input is driven high or low. The WDI input if connected to
a three−stated output device can be disabled in the tristate mode as long as the leakage current is less than 10 mA and a maximum capacitance
of less than 200 pF. To clock the WDI input in the active mode the drive device must be able to source or sink at least 200 mA when active.
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